Tree: 3dfd0cb60d

devel

main

v0.0.1

v0.0.2

v0.0.3

v0.0.4

v0.0.5

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from '3dfd0cb60d'

${ noResults }

Commit Graph

2 Commits (3dfd0cb60dfc01947ae1b9f923795d4ff1490a18)

Author	SHA1	Message	Date
Stefan Holst	aea633ac8d	for release 0.0.5 ... * Techlib: fix NanGate variants * Circuit: more visitor and manipulator utilities * mv_transition: produce stable values when arguments are UNASSIGNED * Verilog: better assign processing * STIL parsing improvements * SDF: conditional parsing (semantics ignored for now), better interconnect annotation, more robust name matching * sim: use ALAP topo-sort * logic_sim: improved fault injection, faster 6V sim * wave_sim: use correct thresholds for pulse filtering, partial delta-sim support, per-sim delay factor * log: fix limiter	4 months ago
Stefan Holst	4bb3f3424a	cond in sdf parser. ignored for now.	2 years ago
Stefan Holst	0c5a7f56e1	Project Import	5 years ago