Commit Graph
160 Commits
Author SHA1 Message Date
Stefan Holst f7ef78e58d support for limiting log messages 2023-07-05 21:59:49 +09:00
Stefan Holst 7afb13b33b mv_str for single values, remove undue assert 2023-07-03 12:40:02 +09:00
Stefan Holst 153442a10a def file parser 2023-07-03 00:49:23 +09:00
Stefan Holst afb0a64953 wsa accumulation in wavesim 2023-07-03 00:48:58 +09:00
Stefan Holst c49667edc1 remove old code, verilog positional pins 2023-06-26 23:23:56 +09:00
Stefan Holst d921eb5048 sim support for remaining primitives 2023-06-25 22:27:19 +09:00
Stefan Holst 670fb0b3fc circuit node substitution 2023-06-25 22:26:52 +09:00
Stefan Holst f8bf579be2 support concat, bus select, ISOL cells 2023-06-24 23:41:08 +09:00
Stefan Holst f61e2b42e8 support more cells in logic sim 2023-06-24 13:34:35 +09:00
Stefan Holst 4aec335abb verilog: concat assignments, more comments 2023-06-24 13:33:55 +09:00
Stefan Holst 1a9cb396bf tweak repr, doc 2023-06-24 13:32:40 +09:00
Stefan Holst 3875dc38f9 docs 2023-06-21 23:23:01 +09:00
Stefan Holst ecb7171c37 docs 2023-06-21 23:18:17 +09:00
Stefan Holst 8957db48ab docs 2023-06-20 06:54:59 +09:00
Stefan Holst 0b15f9fa18 doc improvements 2023-06-19 17:05:39 +09:00
Stefan Holst dc76a9f517 new into demo 2023-06-19 14:01:31 +09:00
Stefan Holst 0968cb451e docs, fix stil unassigned, fix io_locs for busses 2023-06-19 13:12:17 +09:00
Stefan Holst 947df89434 add AOI21 to logic sim 2023-06-02 00:04:34 +09:00
Stefan Holst f17e461fdd fix reading directly from file handle 2023-05-19 14:57:02 +09:00
Stefan Holst d6d981a351 support for det vars 2023-04-05 18:35:55 +09:00
Stefan Holst 7a060b1831 support for static variations 2023-03-28 11:10:38 +09:00
Stefan Holst 03802ac9f8 make sims pickleable 2023-03-22 13:55:53 +09:00
Stefan Holst 70caea065e more cleanup 2023-03-20 14:14:06 +09:00
stefan f04f1b0012 cleanup 2023-03-20 10:31:55 +09:00
Stefan Holst 44b0c887d7 random sampling of delays 2023-03-19 20:30:27 +09:00
Stefan Holst 4e2022291e fix cuda ppo_to_ppi 2023-03-15 15:15:22 +09:00
Stefan Holst 5566b80e52 simprim, vat refactor, batchrange 2023-03-15 10:37:39 +09:00
stefan 63c0b48537 bump 2023-03-14 18:50:15 +09:00
stefan 6520ee23ef cleanup and new intro notebook 2023-03-14 17:40:50 +09:00
stefan 1810d40959 pytest work without cuda 2023-03-13 23:18:32 +09:00
Stefan Holst 7430ebb068 jitted logic sim 2023-03-13 23:15:20 +09:00
stefan 89f317b463 better circuit statsu, 2v logic sim 2023-03-13 10:50:44 +09:00
Stefan Holst 753ce566e4 Timer improvements, log in yaml 2023-03-13 10:45:41 +09:00
stefan 1eb8d87884 faster logic sim, removing MVArray, BPArray 2023-03-12 23:59:10 +09:00
stefan 02f3a0e1b2 correct timing padding 2023-02-28 09:39:01 +09:00
stefan fc8e65e788 bit-packing utility 2023-02-28 09:38:28 +09:00
stefan d80a3ae2b1 timer utility 2023-02-28 09:38:02 +09:00
Stefan Holst 7bfc02e683 more on-gpu code, bump python requirement 2023-02-26 22:37:15 +09:00
Stefan Holst 8da4a62bce switch to new wave_sim, silence occupancy warnings 2023-02-26 13:54:01 +09:00
stefan 3497bfdc75 first gpu-code, cached test fixtures 2023-02-26 13:09:49 +09:00
stefan f1ebe1487c new wave sim 2023-02-26 11:04:38 +09:00
stefan f0dac36ac7 interface -> io_nodes, io_loc fix 2023-02-24 21:56:29 +09:00
Stefan Holst b2953aef25 only dff 2023-02-22 13:37:15 +09:00
Stefan Holst 3774b14286 support ppi/ppo 2023-02-22 13:32:49 +09:00
Stefan Holst 4847ad9c40 locating io ports and busses by name 2023-02-21 23:26:48 +09:00
Stefan Holst 6801606dca new common scheduler for simulators 2023-02-21 19:27:54 +09:00
Stefan Holst faf41f0863 ff transitions switch 2023-02-06 09:53:44 +09:00
Stefan Holst 6430f10f73 HADD pin index fix 2023-02-06 09:52:32 +09:00
Stefan Holst fa19af8c31 4-input gate simulator 2023-01-18 14:34:17 +09:00
Stefan Holst 93a0858d2f oai and aoi pin handling fix 2023-01-16 17:37:41 +09:00