allow interconnect annotations without forks
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795cac0716
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1 file changed
+16
-7
+16
-7
@@ -103,6 +103,7 @@ class DelayFile:
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delays = np.zeros((len(circuit.lines), 2, 2, 3)) # dataset last during construction.
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nonfork_annotations = 0
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for n1, n2, *delvals in self._interconnects:
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delvals = [d if len(d) > 0 else [0, 0, 0] for d in delvals]
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if max(max(delvals)) == 0: continue
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@@ -120,19 +121,27 @@ class DelayFile:
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log.warn(f'No line to annotate pin {pn2} of {c2}')
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continue
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f1, f2 = c1.outs[p1].reader, c2.ins[p2].driver # find the forks between cells.
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if f1 == c2 and f2 == c1:
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nonfork_annotations += 1
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if nonfork_annotations < 10:
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log.warn(f'No fork between {c1.name}/{p1} and {c2.name}/{p2}, using {c2.name}/{p2}')
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line = c2.ins[p2]
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else:
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assert f1.kind == '__fork__'
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assert f2.kind == '__fork__'
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if f1 != f2: # at least two forks, make sure f2 is a branchfork connected to f1
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assert len(f2.outs) == 1
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assert f1.outs[f2.ins[0].driver_pin] == f2.ins[0]
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line = f2.ins[0]
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elif len(f2.outs) == 1: # f1==f2, only OK when there is no fanout.
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if len(f2.outs) == 1:
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assert f1 == f2 or f1.outs[f2.ins[0].driver_pin] == f2.ins[0]
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line = f2.ins[0]
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else:
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log.warn(f'No branchfork to annotate interconnect delay {c1.name}/{p1}->{c2.name}/{p2}')
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continue
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nonfork_annotations += 1
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if nonfork_annotations < 10:
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log.warn(f'No branchfork between {c1.name}/{p1} and {c2.name}/{p2}, using {c2.name}/{p2}')
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line = c2.ins[p2]
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delays[line, :] = delvals
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if nonfork_annotations > 0:
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log.warn(f'{nonfork_annotations} interconnect annotations were moved to gate inputs due to missing forks.')
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return np.moveaxis(delays, -1, 0)
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