use float32 for delays, more robust node-port name splitting

This commit is contained in:
stefan committed 2026-05-27 17:02:42 +09:00
1 parent bd23dfb016
commit f863b70457
1 file changed
+9 -4
+9 -4
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@@ -59,7 +59,7 @@ class DelayFile:
if name not in circuit.cells: name = name.replace('[', '_').replace(']', '_') if name not in circuit.cells: name = name.replace('[', '_').replace(']', '_')
return circuit.cells.get(name, None) return circuit.cells.get(name, None)
delays = np.zeros((len(circuit.lines), 2, 2, 3)) # dataset last during construction. delays = np.zeros((len(circuit.lines), 2, 2, 3), dtype=np.float32) # dataset last during construction.
with log.limit(50): with log.limit(50):
for name, iopaths in self.cells.items(): for name, iopaths in self.cells.items():
@@ -101,14 +101,19 @@ class DelayFile:
* Axis 3: polarity of the transition, 0='rising/posedge', 1='falling/negedge' * Axis 3: polarity of the transition, 0='rising/posedge', 1='falling/negedge'
""" """
delays = np.zeros((len(circuit.lines), 2, 2, 3)) # dataset last during construction. delays = np.zeros((len(circuit.lines), 2, 2, 3), dtype=np.float32) # dataset last during construction.
def split_node_port(n_str):
if (split := n_str.rfind('.')) > 0 or (split := n_str.rfind('/')) > 0:
return n_str[:split], n_str[split+1:]
return (n_str, None)
nonfork_annotations = 0 nonfork_annotations = 0
for n1, n2, *delvals in self._interconnects: for n1, n2, *delvals in self._interconnects:
delvals = [d if len(d) > 0 else [0, 0, 0] for d in delvals] delvals = [d if len(d) > 0 else [0, 0, 0] for d in delvals]
if max(max(delvals)) == 0: continue if max(max(delvals)) == 0: continue
cn1, pn1 = (n1, None) if (slash := n1.rfind('/')) < 0 else (n1[:slash], n1[slash+1:]) cn1, pn1 = split_node_port(n1)
cn2, pn2 = (n2, None) if (slash := n2.rfind('/')) < 0 else (n2[:slash], n2[slash+1:]) cn2, pn2 = split_node_port(n2)
cn1 = cn1.replace('\\','') cn1 = cn1.replace('\\','')
cn2 = cn2.replace('\\','') cn2 = cn2.replace('\\','')
c1, c2 = circuit.cells[cn1], circuit.cells[cn2] c1, c2 = circuit.cells[cn1], circuit.cells[cn2]