diff --git a/src/kyupy/logic_sim.py b/src/kyupy/logic_sim.py
index 21bc4a9..3ac5233 100644
--- a/src/kyupy/logic_sim.py
+++ b/src/kyupy/logic_sim.py
@@ -52,7 +52,7 @@ class LogicSim(sim.SimOps):
         """
         self.c[self.pippi_c_locs] = self.s[0, self.pippi_s_locs, :self.mdim]
 
-    def c_prop(self, sims=None, inject_cb=None, flip_line=-1, flip_mask=None):
+    def c_prop(self, sims=None, inject_cb=None, fault_line=-1, fault_mask=None, fault_model=2):
         """Propagate the input values through the combinational circuit towards the outputs.
 
         Performs all logic operations in topological order.
@@ -68,14 +68,14 @@ class LogicSim(sim.SimOps):
         t1 = self.c_locs[self.tmp2_idx]
         if self.m == 2:
             if inject_cb is None:
-                if flip_mask is None:
-                    flip_mask = np.full(self.c.shape[-1], 255, dtype=np.uint8)
+                if fault_mask is None:
+                    fault_mask = np.full(self.c.shape[-1], 255, dtype=np.uint8)
                 else:
-                    if len(flip_mask) < self.c.shape[-1]:
-                        flip_mask2 = np.full(self.c.shape[-1], 0, dtype=np.uint8)
-                        flip_mask2[:len(flip_mask)] = flip_mask
-                        flip_mask = flip_mask2
-                _prop_cpu(self.ops, self.c_locs, self.c, int(flip_line), flip_mask)
+                    if len(fault_mask) < self.c.shape[-1]:
+                        fault_mask2 = np.full(self.c.shape[-1], 0, dtype=np.uint8)
+                        fault_mask2[:len(fault_mask)] = fault_mask
+                        fault_mask = fault_mask2
+                _prop_cpu(self.ops, self.c_locs, self.c, int(fault_line), fault_mask, int(fault_model))
             else:
                 for op, o0l, i0l, i1l, i2l, i3l in self.ops[:,:6]:
                     o0, i0, i1, i2, i3 = [self.c_locs[x] for x in (o0l, i0l, i1l, i2l, i3l)]
@@ -305,7 +305,7 @@ class LogicSim(sim.SimOps):
 
 
 @numba.njit
-def _prop_cpu(ops, c_locs, c, flip_line, flip_mask):
+def _prop_cpu(ops, c_locs, c, fault_line, fault_mask, fault_model):
     for op, o0l, i0l, i1l, i2l, i3l in ops[:,:6]:
         o0, i0, i1, i2, i3 = [c_locs[x] for x in (o0l, i0l, i1l, i2l, i3l)]
         if op == sim.BUF1: c[o0]=c[i0]
@@ -342,9 +342,14 @@ def _prop_cpu(ops, c_locs, c, flip_line, flip_mask):
         elif op == sim.OAI211: c[o0] = ~((c[i0] | c[i1]) & c[i2] & c[i3])
         elif op == sim.MUX21: c[o0] = (c[i0] & ~c[i2]) | (c[i1] & c[i2])
         else: print(f'unknown op {op}')
-        if flip_line >= 0 and o0l == flip_line:
-            #n = len(flip_mask)
-            c[o0] = c[o0] ^ flip_mask
+        if fault_line >= 0 and o0l == fault_line:
+            #n = len(fault_mask)
+            if fault_model == 0:
+                c[o0] = c[o0] & ~fault_mask
+            elif fault_model == 1:
+                c[o0] = c[o0] | fault_mask
+            else:
+                c[o0] = c[o0] ^ fault_mask
 
 
 class LogicSim6V(sim.SimOps):