let SimOps refuse building broken sim models.
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+4
-7
@@ -160,7 +160,7 @@ class SimOps:
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"""A static scheduler that translates a Circuit into a topologically sorted list of basic logic operations (self.ops) and
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a memory mapping (self.c_locs, self.c_caps) for use in simulators.
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:param circuit: The circuit to create a schedule for.
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:param circuit: The circuit to create a schedule for. Must contain cells from KYUPY techlib only.
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:param strip_forks: If enabled, the scheduler will not include fork nodes to safe simulation time.
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Stripping forks will cause interconnect delay annotations of lines read by fork nodes to be ignored.
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:param c_reuse: If enabled, memory of intermediate signal waveforms will be re-used. This greatly reduces
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@@ -201,8 +201,7 @@ class SimOps:
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for l in level_lines:
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n = l.driver
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if len(n.ins) > 4:
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log.warn(f'too many input pins: {n}')
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assert len(n.ins) <= 4, f'Too many input pins for node {n}. Map circuit to KYUPY techlib first using resolce_tlib_cells().'
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in_idxs = [n.ins[x].index if len(n.ins) > x and n.ins[x] is not None else self.zero_idx for x in [0,1,2,3]]
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if n in ppio2idx:
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in_idxs[0] = self.ppi_offset + ppio2idx[n]
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@@ -226,10 +225,8 @@ class SimOps:
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if in_idxs[2] == self.zero_idx:
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sp = prims[2]
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break
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if sp is None:
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log.warn(f'ignored cell of unknown type: {n}')
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else:
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level_ops.append((sp, l.index, *in_idxs, *a_ctrl[l]))
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assert sp is not None, f'Unsupported node type {n}. Map circuit to KYUPY techlib first using resolce_tlib_cells().'
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level_ops.append((sp, l.index, *in_idxs, *a_ctrl[l]))
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if len(level_ops) > 0: levels.append(level_ops)
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level_lines = prev_level_lines
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