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let SimOps refuse building broken sim models.

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stefan committed 2026-06-21 09:26:03 +09:00
1 parent 3a2cfb7788
commit e7b5567d87
1 file changed
+4 -7
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src/kyupy/sim.py
+4 -7
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@@ -160,7 +160,7 @@ class SimOps:
"""A static scheduler that translates a Circuit into a topologically sorted list of basic logic operations (self.ops) and """A static scheduler that translates a Circuit into a topologically sorted list of basic logic operations (self.ops) and
a memory mapping (self.c_locs, self.c_caps) for use in simulators. a memory mapping (self.c_locs, self.c_caps) for use in simulators.
:param circuit: The circuit to create a schedule for. :param circuit: The circuit to create a schedule for. Must contain cells from KYUPY techlib only.
:param strip_forks: If enabled, the scheduler will not include fork nodes to safe simulation time. :param strip_forks: If enabled, the scheduler will not include fork nodes to safe simulation time.
Stripping forks will cause interconnect delay annotations of lines read by fork nodes to be ignored. Stripping forks will cause interconnect delay annotations of lines read by fork nodes to be ignored.
:param c_reuse: If enabled, memory of intermediate signal waveforms will be re-used. This greatly reduces :param c_reuse: If enabled, memory of intermediate signal waveforms will be re-used. This greatly reduces
@@ -201,8 +201,7 @@ class SimOps:
for l in level_lines: for l in level_lines:
n = l.driver n = l.driver
if len(n.ins) > 4: assert len(n.ins) <= 4, f'Too many input pins for node {n}. Map circuit to KYUPY techlib first using resolce_tlib_cells().'
log.warn(f'too many input pins: {n}')
in_idxs = [n.ins[x].index if len(n.ins) > x and n.ins[x] is not None else self.zero_idx for x in [0,1,2,3]] in_idxs = [n.ins[x].index if len(n.ins) > x and n.ins[x] is not None else self.zero_idx for x in [0,1,2,3]]
if n in ppio2idx: if n in ppio2idx:
in_idxs[0] = self.ppi_offset + ppio2idx[n] in_idxs[0] = self.ppi_offset + ppio2idx[n]
@@ -226,10 +225,8 @@ class SimOps:
if in_idxs[2] == self.zero_idx: if in_idxs[2] == self.zero_idx:
sp = prims[2] sp = prims[2]
break break
if sp is None: assert sp is not None, f'Unsupported node type {n}. Map circuit to KYUPY techlib first using resolce_tlib_cells().'
log.warn(f'ignored cell of unknown type: {n}') level_ops.append((sp, l.index, *in_idxs, *a_ctrl[l]))
else:
level_ops.append((sp, l.index, *in_idxs, *a_ctrl[l]))
if len(level_ops) > 0: levels.append(level_ops) if len(level_ops) > 0: levels.append(level_ops)
level_lines = prev_level_lines level_lines = prev_level_lines