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@ -51,6 +51,7 @@ class LogicSim(sim.SimOps): |
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nbytes = cdiv(sims, 8) |
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nbytes = cdiv(sims, 8) |
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self.c = np.zeros((self.c_len, self.mdim, nbytes), dtype=np.uint8) |
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self.c = np.zeros((self.c_len, self.mdim, nbytes), dtype=np.uint8) |
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self.c_dirty = np.full(self.c_len, 1, dtype=np.uint8) |
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self.s = np.zeros((2, self.s_len, 3, nbytes), dtype=np.uint8) |
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self.s = np.zeros((2, self.s_len, 3, nbytes), dtype=np.uint8) |
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"""Logic values of the sequential elements (flip-flops) and ports. |
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"""Logic values of the sequential elements (flip-flops) and ports. |
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@ -97,7 +98,7 @@ class LogicSim(sim.SimOps): |
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t1 = self.c_locs[self.tmp2_idx] |
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t1 = self.c_locs[self.tmp2_idx] |
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if self.m == 2: |
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if self.m == 2: |
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if inject_cb is None: |
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if inject_cb is None: |
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c_prop_2v_cpu(self.ops, self.c_locs, self.c, int(fault_line), fault_mask, int(fault_model)) |
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c_prop_2v_cpu(self.ops, self.c_locs, self.c, self.c_dirty, int(fault_line), fault_mask, int(fault_model)) |
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else: |
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else: |
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for op, o0l, i0l, i1l, i2l, i3l in self.ops[:,:6]: |
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for op, o0l, i0l, i1l, i2l, i3l in self.ops[:,:6]: |
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o0, i0, i1, i2, i3 = [self.c_locs[x] for x in (o0l, i0l, i1l, i2l, i3l)] |
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o0, i0, i1, i2, i3 = [self.c_locs[x] for x in (o0l, i0l, i1l, i2l, i3l)] |
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