From df695e0aa1ab76eb383a50043185cfadc807c5ff Mon Sep 17 00:00:00 2001 From: Stefan Holst Date: Thu, 27 Nov 2025 21:35:31 +0900 Subject: [PATCH] for release 0.0.6 - sim: added LogicSim2V, LogicSim4V, LogicSim6V (faster and simpler API) - sim: fixed model for: many-input gates in bench; dangling nodes; POs that drive further logic - Circuit: dot output fix and better style, fixed equivalence check of lines and nodes. - Techlib: Added KYUPY library with supported simulation primitives for debug and testing - tests: fixed and added more for better coverage - more type annotations - updated project config and dependencies for better uv experience, newer lark, newer numpy --- docs/simulators.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/docs/simulators.rst b/docs/simulators.rst index 44360f7..487ac1f 100644 --- a/docs/simulators.rst +++ b/docs/simulators.rst @@ -14,6 +14,15 @@ Logic Simulation - :mod:`kyupy.logic_sim` .. autoclass:: kyupy.logic_sim.LogicSim :members: +.. autoclass:: kyupy.logic_sim.LogicSim2V + :members: + +.. autoclass:: kyupy.logic_sim.LogicSim4V + :members: + +.. autoclass:: kyupy.logic_sim.LogicSim6V + :members: + Timing Simulation - :mod:`kyupy.wave_sim` -----------------------------------------