fix log limiter, use eng notation
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4 files changed
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-21
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+15
-3
@@ -57,6 +57,18 @@ def hr_bytes(nbytes):
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multiplier += 1
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multiplier += 1
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return f'{nbytes:.1f}{["", "ki", "Mi", "Gi", "Ti", "Pi"][multiplier]}B'
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return f'{nbytes:.1f}{["", "ki", "Mi", "Gi", "Ti", "Pi"][multiplier]}B'
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def eng(number):
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"""Formats a given number using engineering notation."""
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exponent = 0
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if abs(number) < 1:
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while abs(number) >= 1000:
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number *= 1000
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exponent -= 3
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else:
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while abs(number) >= 1000:
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number /= 1000
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exponent += 3
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return f'{number:.0f}' + (f'e{exponent}' if exponent != 0 else '')
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def hr_time(seconds):
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def hr_time(seconds):
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"""Formats a given time interval for human readability."""
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"""Formats a given time interval for human readability."""
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@@ -138,10 +150,10 @@ class Log:
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self._limit = limit
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self._limit = limit
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def stop_limit(self):
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def stop_limit(self):
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if self.filtered > 0:
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log.info(f'{self.filtered} more messages (filtered).')
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self.filtered = 0
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self._limit = -1
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self._limit = -1
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if self.filtered > 0:
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self.info(f'{self.filtered} more messages (filtered).')
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self.filtered = 0
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def __getstate__(self):
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def __getstate__(self):
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return {'elapsed': time.perf_counter() - self.start}
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return {'elapsed': time.perf_counter() - self.start}
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@@ -10,7 +10,7 @@ import math
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import numpy as np
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import numpy as np
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from . import numba, logic, hr_bytes, sim
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from . import numba, logic, hr_bytes, sim, eng
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from .circuit import Circuit
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from .circuit import Circuit
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class LogicSim(sim.SimOps):
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class LogicSim(sim.SimOps):
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@@ -44,7 +44,7 @@ class LogicSim(sim.SimOps):
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self.s[:,:,1,:] = 255 # unassigned
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self.s[:,:,1,:] = 255 # unassigned
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def __repr__(self):
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def __repr__(self):
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return f'{{name: "{self.circuit.name}", sims: {self.sims}, m: {self.m}, c_bytes: {self.c.nbytes}}}'
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return f'{{name: "{self.circuit.name}", sims: {self.sims}, m: {self.m}, c_bytes: {eng(self.c.nbytes)}}}'
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def s_to_c(self):
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def s_to_c(self):
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"""Copies the values from ``s[0]`` the inputs of the combinational portion.
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"""Copies the values from ``s[0]`` the inputs of the combinational portion.
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+15
-14
@@ -61,20 +61,21 @@ class DelayFile:
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delays = np.zeros((len(circuit.lines), 2, 2, 3)) # dataset last during construction.
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delays = np.zeros((len(circuit.lines), 2, 2, 3)) # dataset last during construction.
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for name, iopaths in self.cells.items():
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with log.limit(50):
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name = name.replace('\\', '')
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for name, iopaths in self.cells.items():
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if cell := circuit.cells.get(name, None):
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name = name.replace('\\', '')
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for i_pin_spec, o_pin_spec, *dels in iopaths:
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if cell := circuit.cells.get(name, None):
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if i_pin_spec.startswith('(posedge '): i_pol_idxs = [0]
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for i_pin_spec, o_pin_spec, *dels in iopaths:
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elif i_pin_spec.startswith('(negedge '): i_pol_idxs = [1]
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if i_pin_spec.startswith('(posedge '): i_pol_idxs = [0]
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else: i_pol_idxs = [0, 1]
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elif i_pin_spec.startswith('(negedge '): i_pol_idxs = [1]
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i_pin_spec = re.sub(r'\((neg|pos)edge ([^)]+)\)', r'\2', i_pin_spec)
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else: i_pol_idxs = [0, 1]
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if line := cell.ins[tlib.pin_index(cell.kind, i_pin_spec)]:
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i_pin_spec = re.sub(r'\((neg|pos)edge ([^)]+)\)', r'\2', i_pin_spec)
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delays[line, i_pol_idxs] = [d if len(d) > 0 else [0, 0, 0] for d in dels]
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if line := cell.ins[tlib.pin_index(cell.kind, i_pin_spec)]:
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else:
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delays[line, i_pol_idxs] = [d if len(d) > 0 else [0, 0, 0] for d in dels]
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log.warn(f'No line to annotate in circuit: {i_pin_spec} for {cell}')
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else:
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else:
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log.warn(f'No line to annotate in circuit: {i_pin_spec} for {cell}')
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log.warn(f'Name from SDF not found in circuit: {name}')
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else:
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log.warn(f'Name from SDF not found in circuit: {name}')
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return np.moveaxis(delays, -1, 0)
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return np.moveaxis(delays, -1, 0)
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@@ -16,7 +16,7 @@ import math
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import numpy as np
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import numpy as np
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from . import numba, cuda, sim, cdiv
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from . import numba, cuda, sim, cdiv, eng
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TMAX = np.float32(2 ** 127)
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TMAX = np.float32(2 ** 127)
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@@ -103,7 +103,7 @@ class WaveSim(sim.SimOps):
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def __repr__(self):
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def __repr__(self):
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dev = 'GPU' if hasattr(self.c, 'copy_to_host') else 'CPU'
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dev = 'GPU' if hasattr(self.c, 'copy_to_host') else 'CPU'
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return f'{{name: "{self.circuit.name}", device: "{dev}", sims: {self.sims}, ops: {len(self.ops)}, ' + \
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return f'{{name: "{self.circuit.name}", device: "{dev}", sims: {self.sims}, ops: {len(self.ops)}, ' + \
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f'levels: {len(self.level_starts)}, nbytes: {self.nbytes}}}'
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f'levels: {len(self.level_starts)}, nbytes: {eng(self.nbytes)}}}'
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def s_to_c(self):
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def s_to_c(self):
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"""Transfers values of sequential elements and primary inputs to the combinational portion.
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"""Transfers values of sequential elements and primary inputs to the combinational portion.
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