fix log limiter, use eng notation

This commit is contained in:
Stefan Holst committed 2023-09-26 13:58:38 +09:00
1 parent 4bb3f3424a
commit de79393dfc
4 files changed
+34 -21

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+15 -3
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@@ -57,6 +57,18 @@ def hr_bytes(nbytes):
multiplier += 1 multiplier += 1
return f'{nbytes:.1f}{["", "ki", "Mi", "Gi", "Ti", "Pi"][multiplier]}B' return f'{nbytes:.1f}{["", "ki", "Mi", "Gi", "Ti", "Pi"][multiplier]}B'
def eng(number):
"""Formats a given number using engineering notation."""
exponent = 0
if abs(number) < 1:
while abs(number) >= 1000:
number *= 1000
exponent -= 3
else:
while abs(number) >= 1000:
number /= 1000
exponent += 3
return f'{number:.0f}' + (f'e{exponent}' if exponent != 0 else '')
def hr_time(seconds): def hr_time(seconds):
"""Formats a given time interval for human readability.""" """Formats a given time interval for human readability."""
@@ -138,10 +150,10 @@ class Log:
self._limit = limit self._limit = limit
def stop_limit(self): def stop_limit(self):
if self.filtered > 0:
log.info(f'{self.filtered} more messages (filtered).')
self.filtered = 0
self._limit = -1 self._limit = -1
if self.filtered > 0:
self.info(f'{self.filtered} more messages (filtered).')
self.filtered = 0
def __getstate__(self): def __getstate__(self):
return {'elapsed': time.perf_counter() - self.start} return {'elapsed': time.perf_counter() - self.start}
+2 -2
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@@ -10,7 +10,7 @@ import math
import numpy as np import numpy as np
from . import numba, logic, hr_bytes, sim from . import numba, logic, hr_bytes, sim, eng
from .circuit import Circuit from .circuit import Circuit
class LogicSim(sim.SimOps): class LogicSim(sim.SimOps):
@@ -44,7 +44,7 @@ class LogicSim(sim.SimOps):
self.s[:,:,1,:] = 255 # unassigned self.s[:,:,1,:] = 255 # unassigned
def __repr__(self): def __repr__(self):
return f'{{name: "{self.circuit.name}", sims: {self.sims}, m: {self.m}, c_bytes: {self.c.nbytes}}}' return f'{{name: "{self.circuit.name}", sims: {self.sims}, m: {self.m}, c_bytes: {eng(self.c.nbytes)}}}'
def s_to_c(self): def s_to_c(self):
"""Copies the values from ``s[0]`` the inputs of the combinational portion. """Copies the values from ``s[0]`` the inputs of the combinational portion.
+15 -14
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@@ -61,20 +61,21 @@ class DelayFile:
delays = np.zeros((len(circuit.lines), 2, 2, 3)) # dataset last during construction. delays = np.zeros((len(circuit.lines), 2, 2, 3)) # dataset last during construction.
for name, iopaths in self.cells.items(): with log.limit(50):
name = name.replace('\\', '') for name, iopaths in self.cells.items():
if cell := circuit.cells.get(name, None): name = name.replace('\\', '')
for i_pin_spec, o_pin_spec, *dels in iopaths: if cell := circuit.cells.get(name, None):
if i_pin_spec.startswith('(posedge '): i_pol_idxs = [0] for i_pin_spec, o_pin_spec, *dels in iopaths:
elif i_pin_spec.startswith('(negedge '): i_pol_idxs = [1] if i_pin_spec.startswith('(posedge '): i_pol_idxs = [0]
else: i_pol_idxs = [0, 1] elif i_pin_spec.startswith('(negedge '): i_pol_idxs = [1]
i_pin_spec = re.sub(r'\((neg|pos)edge ([^)]+)\)', r'\2', i_pin_spec) else: i_pol_idxs = [0, 1]
if line := cell.ins[tlib.pin_index(cell.kind, i_pin_spec)]: i_pin_spec = re.sub(r'\((neg|pos)edge ([^)]+)\)', r'\2', i_pin_spec)
delays[line, i_pol_idxs] = [d if len(d) > 0 else [0, 0, 0] for d in dels] if line := cell.ins[tlib.pin_index(cell.kind, i_pin_spec)]:
else: delays[line, i_pol_idxs] = [d if len(d) > 0 else [0, 0, 0] for d in dels]
log.warn(f'No line to annotate in circuit: {i_pin_spec} for {cell}') else:
else: log.warn(f'No line to annotate in circuit: {i_pin_spec} for {cell}')
log.warn(f'Name from SDF not found in circuit: {name}') else:
log.warn(f'Name from SDF not found in circuit: {name}')
return np.moveaxis(delays, -1, 0) return np.moveaxis(delays, -1, 0)
+2 -2
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@@ -16,7 +16,7 @@ import math
import numpy as np import numpy as np
from . import numba, cuda, sim, cdiv from . import numba, cuda, sim, cdiv, eng
TMAX = np.float32(2 ** 127) TMAX = np.float32(2 ** 127)
@@ -103,7 +103,7 @@ class WaveSim(sim.SimOps):
def __repr__(self): def __repr__(self):
dev = 'GPU' if hasattr(self.c, 'copy_to_host') else 'CPU' dev = 'GPU' if hasattr(self.c, 'copy_to_host') else 'CPU'
return f'{{name: "{self.circuit.name}", device: "{dev}", sims: {self.sims}, ops: {len(self.ops)}, ' + \ return f'{{name: "{self.circuit.name}", device: "{dev}", sims: {self.sims}, ops: {len(self.ops)}, ' + \
f'levels: {len(self.level_starts)}, nbytes: {self.nbytes}}}' f'levels: {len(self.level_starts)}, nbytes: {eng(self.nbytes)}}}'
def s_to_c(self): def s_to_c(self):
"""Transfers values of sequential elements and primary inputs to the combinational portion. """Transfers values of sequential elements and primary inputs to the combinational portion.