From da98ca2db7504692a7d64d10c2724e58af234e8b Mon Sep 17 00:00:00 2001 From: Stefan Holst Date: Wed, 10 Apr 2024 19:27:06 +0900 Subject: [PATCH] signal flips in compiled code --- src/kyupy/logic_sim.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/kyupy/logic_sim.py b/src/kyupy/logic_sim.py index 26c361f..208ea5a 100644 --- a/src/kyupy/logic_sim.py +++ b/src/kyupy/logic_sim.py @@ -52,7 +52,7 @@ class LogicSim(sim.SimOps): """ self.c[self.pippi_c_locs] = self.s[0, self.pippi_s_locs, :self.mdim] - def c_prop(self, sims=None, inject_cb=None): + def c_prop(self, sims=None, inject_cb=None, flip_line=-1): """Propagate the input values through the combinational circuit towards the outputs. Performs all logic operations in topological order. @@ -68,7 +68,7 @@ class LogicSim(sim.SimOps): t1 = self.c_locs[self.tmp2_idx] if self.m == 2: if inject_cb is None: - _prop_cpu(self.ops, self.c_locs, self.c) + _prop_cpu(self.ops, self.c_locs, self.c, int(flip_line)) else: for op, o0l, i0l, i1l, i2l, i3l in self.ops[:,:6]: o0, i0, i1, i2, i3 = [self.c_locs[x] for x in (o0l, i0l, i1l, i2l, i3l)] @@ -298,9 +298,9 @@ class LogicSim(sim.SimOps): @numba.njit -def _prop_cpu(ops, c_locs, c): - for op, o0, i0, i1, i2, i3 in ops[:,:6]: - o0, i0, i1, i2, i3 = [c_locs[x] for x in (o0, i0, i1, i2, i3)] +def _prop_cpu(ops, c_locs, c, flip_line): + for op, o0l, i0l, i1l, i2l, i3l in ops[:,:6]: + o0, i0, i1, i2, i3 = [c_locs[x] for x in (o0l, i0l, i1l, i2l, i3l)] if op == sim.BUF1: c[o0]=c[i0] elif op == sim.INV1: c[o0] = ~c[i0] elif op == sim.AND2: c[o0] = c[i0] & c[i1] @@ -335,6 +335,8 @@ def _prop_cpu(ops, c_locs, c): elif op == sim.OAI211: c[o0] = ~((c[i0] | c[i1]) & c[i2] & c[i3]) elif op == sim.MUX21: c[o0] = (c[i0] & ~c[i2]) | (c[i1] & c[i2]) else: print(f'unknown op {op}') + if flip_line >= 0 and o0l == flip_line: + c[o0] = ~c[o0] class LogicSim6V(sim.SimOps):