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for release 0.0.6

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- sim: added LogicSim2V, LogicSim4V, LogicSim6V (faster and simpler API)
- sim: fixed model for: many-input gates in bench; dangling nodes; POs that drive further logic
- Circuit: dot output fix and better style, fixed equivalence check of lines and nodes.
- Techlib: Added KYUPY library with supported simulation primitives for debug and testing
- tests: fixed and added more for better coverage
- more type annotations
- updated project config and dependencies for better uv experience, newer lark, newer numpy
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stefan committed 2025-11-27 21:35:45 +09:00
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docs/Makefile
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# pip install sphinx sphinx-rtd-theme
# pip install sphinx sphinx-rtd-theme myst-parser
#
# Minimal makefile for Sphinx documentation
#