for release 0.0.6

- sim: added LogicSim2V, LogicSim4V, LogicSim6V (faster and simpler API)
- sim: fixed model for: many-input gates in bench; dangling nodes; POs that drive further logic
- Circuit: dot output fix and better style, fixed equivalence check of lines and nodes.
- Techlib: Added KYUPY library with supported simulation primitives for debug and testing
- tests: fixed and added more for better coverage
- more type annotations
- updated project config and dependencies for better uv experience, newer lark, newer numpy

docs/Makefile

@@ -1,4 +1,4 @@
-# pip install sphinx sphinx-rtd-theme
+# pip install sphinx sphinx-rtd-theme myst-parser
 #
 # Minimal makefile for Sphinx documentation
 #

docs/conf.py

@@ -20,11 +20,11 @@ sys.path.insert(0, os.path.abspath('../src'))
 # -- Project information -----------------------------------------------------
 
 project = 'KyuPy'
-copyright = '2020-2023, Stefan Holst'
+copyright = '2020-2025, Stefan Holst'
 author = 'Stefan Holst'
 
 # The full version, including alpha/beta/rc tags
-release = '0.0.5'
+release = '0.0.6'
 
 
 # -- General configuration ---------------------------------------------------
@@ -35,6 +35,7 @@ release = '0.0.5'
 extensions = [
     'sphinx.ext.autodoc',
     'sphinx_rtd_theme',
+    'myst_parser',
 ]
 
 # Add any paths that contain templates here, relative to this directory.

docs/index.rst

@@ -1,4 +1,5 @@
-.. include:: ../README.rst
+.. include:: ../README.md
+   :parser: myst_parser.sphinx_
 
 API Reference
 -------------

docs/simulators.rst

@@ -14,6 +14,15 @@ Logic Simulation - :mod:`kyupy.logic_sim`
 .. autoclass:: kyupy.logic_sim.LogicSim
    :members:
 
+.. autoclass:: kyupy.logic_sim.LogicSim2V
+   :members:
+
+.. autoclass:: kyupy.logic_sim.LogicSim4V
+   :members:
+
+.. autoclass:: kyupy.logic_sim.LogicSim6V
+   :members:
+
 
 Timing Simulation - :mod:`kyupy.wave_sim`
 -----------------------------------------