remove old code, verilog positional pins
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Stefan Holst committed
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d921eb5048
commit
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2 files changed
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-261
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+21
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@@ -1,6 +1,7 @@
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from .circuit import Node, Line
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from .circuit import Node, Line
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from . import bench
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from . import bench
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def add_and_connect(circuit, name, kind, in1=None, in2=None, out=None):
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def add_and_connect(circuit, name, kind, in1=None, in2=None, out=None):
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n = Node(circuit, name, kind)
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n = Node(circuit, name, kind)
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if in1 is not None:
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if in1 is not None:
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@@ -29,6 +30,8 @@ class TechLib:
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@staticmethod
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@staticmethod
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def pin_index(kind, pin):
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def pin_index(kind, pin):
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"""Returns a pin list position for a given node kind and pin name."""
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"""Returns a pin list position for a given node kind and pin name."""
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if isinstance(pin, int):
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return max(0, pin-1)
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if kind[:3] in ('OAI', 'AOI'):
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if kind[:3] in ('OAI', 'AOI'):
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if pin[0] == 'A': return int(pin[1]) - 1
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if pin[0] == 'A': return int(pin[1]) - 1
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if pin == 'B': return int(kind[3])
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if pin == 'B': return int(kind[3])
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@@ -63,270 +66,31 @@ class TechLib:
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@staticmethod
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@staticmethod
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def pin_is_output(kind, pin):
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def pin_is_output(kind, pin):
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"""Returns True, if given pin name of a node kind is an output."""
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"""Returns True, if given pin name of a node kind is an output."""
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if isinstance(pin, int):
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return pin == 0
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if 'MUX' in kind and pin == 'S': return False
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if 'MUX' in kind and pin == 'S': return False
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return pin in ('Q', 'QN', 'Z', 'ZN', 'Y', 'CO', 'S', 'SO', 'C1')
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return pin in ('Q', 'QN', 'Z', 'ZN', 'Y', 'CO', 'S', 'SO', 'C1')
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@staticmethod
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@staticmethod
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def substitute_nonsim_cells(circuit):
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def substitute_nonsim_cells(circuit):
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tmap = {'ISOLAND': bench.parse('input(iso, d) output(q) not_iso=not(iso) q=and(not_iso, d)'),
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tmap = {'ISOLAND': bench.parse('input(iso, d) output(q) not_iso=not(iso) q=and(not_iso, d)'),
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'AO221' : bench.parse('input(in1, in2, in3, in4, in5) output(q) a=ao22(in1, in2, in3, in4) q=or(a, in5)'),
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'AO221' : bench.parse('input(in1,in2,in3,in4,in5) output(q) a=ao22(in1, in2, in3, in4) q=or(a, in5)'),
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'AOI221' : bench.parse('input(in1, in2, in3, in4, in5) output(qn) a=ao22(in1, in2, in3, in4) qn=nor(a, in5)'),
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'AOI221' : bench.parse('input(in1,in2,in3,in4,in5) output(qn) a=ao22(in1, in2, in3, in4) qn=nor(a, in5)'),
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'OA221' : bench.parse('input(in1, in2, in3, in4, in5) output(q) a=oa22(in1, in2, in3, in4) q=and(a, in5)'),
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'OA221' : bench.parse('input(in1,in2,in3,in4,in5) output(q) a=oa22(in1, in2, in3, in4) q=and(a, in5)'),
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'OAI221' : bench.parse('input(in1, in2, in3, in4, in5) output(qn) a=oa22(in1, in2, in3, in4) qn=nand(a, in5)'),
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'OAI221' : bench.parse('input(in1,in2,in3,in4,in5) output(qn) a=oa22(in1, in2, in3, in4) qn=nand(a, in5)'),
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'AO222' : bench.parse('input(in1, in2, in3, in4, in5, in6) output(q) a=ao22(in1, in2, in3, in4) q=ao21(in5, in6, a)'),
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'AO222' : bench.parse('input(in1,in2,in3,in4,in5,in6) output(q) a=ao22(in1, in2, in3, in4) q=ao21(in5, in6, a)'),
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'AOI222' : bench.parse('input(in1, in2, in3, in4, in5, in6) output(qn) a=ao22(in1, in2, in3, in4) qn=aoi21(in5, in6, a)'),
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'AOI222' : bench.parse('input(in1,in2,in3,in4,in5,in6) output(qn) a=ao22(in1, in2, in3, in4) qn=aoi21(in5, in6, a)'),
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'OA222' : bench.parse('input(in1, in2, in3, in4, in5, in6) output(q) a=oa22(in1, in2, in3, in4) q=oa21(in5, in6, a)'),
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'OA222' : bench.parse('input(in1,in2,in3,in4,in5,in6) output(q) a=oa22(in1, in2, in3, in4) q=oa21(in5, in6, a)'),
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'OAI222' : bench.parse('input(in1, in2, in3, in4, in5, in6) output(qn) a=oa22(in1, in2, in3, in4) qn=oai21(in5, in6, a)'),
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'OAI222' : bench.parse('input(in1,in2,in3,in4,in5,in6) output(qn) a=oa22(in1, in2, in3, in4) qn=oai21(in5, in6, a)'),
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'HADD' : bench.parse('input(a,b) output(s,co) co=xor(a,b) s=and(a,b)'),
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'FADD' : bench.parse('input(a,b,ci) output(s,co) ab=xor(a,b) co=xor(ab,ci) s=ao22(ab,ci,a,b)'),
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}
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}
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for n in list(circuit.nodes):
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for n in list(circuit.nodes):
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for k, v in tmap.items():
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if n.kind.startswith('DFFSSR'):
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if n.kind.startswith(k):
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circuit.substitute(n, v)
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@staticmethod
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def split_complex_gates(circuit):
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node_list = circuit.nodes
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for n in node_list:
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name = n.name
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ins = n.ins
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outs = n.outs
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if n.kind.startswith('AO21X'):
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n.remove()
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n_and = add_and_connect(circuit, name+'~and', 'AND2', ins[0], ins[1], None)
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n_or = add_and_connect(circuit, name+'~or', 'OR2', None, ins[2], outs[0])
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Line(circuit, n_and, n_or)
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elif n.kind.startswith('AOI21X'):
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n.remove()
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n_and = add_and_connect(circuit, name+'~and', 'AND2', ins[0], ins[1], None)
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n_nor = add_and_connect(circuit, name+'~nor', 'NOR2', None, ins[2], outs[0])
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Line(circuit, n_and, n_nor)
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elif n.kind.startswith('OA21X'):
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n.remove()
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n_or = add_and_connect(circuit, name+'~or', 'OR2', ins[0], ins[1], None)
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n_and = add_and_connect(circuit, name+'~and', 'AND2', None, ins[2], outs[0])
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Line(circuit, n_or, n_and)
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elif n.kind.startswith('OAI21X'):
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n.remove()
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n_or = add_and_connect(circuit, name+'~or', 'OR2', ins[0], ins[1], None)
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n_nand = add_and_connect(circuit, name+'~nand', 'NAND2', None, ins[2], outs[0])
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Line(circuit, n_or, n_nand)
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elif n.kind.startswith('OA22X'):
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n.remove()
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n_or0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n_or1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
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n_and = add_and_connect(circuit, name+'~and', 'AND2', None, None, outs[0])
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Line(circuit, n_or0, n_and)
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Line(circuit, n_or1, n_and)
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elif n.kind.startswith('OAI22X'):
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n.remove()
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n_or0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n_or1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
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n_nand = add_and_connect(circuit, name+'~nand', 'NAND2', None, None, outs[0])
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Line(circuit, n_or0, n_nand)
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Line(circuit, n_or1, n_nand)
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elif n.kind.startswith('AO22X'):
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n.remove()
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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n_and1 = add_and_connect(circuit, name+'~and1', 'AND2', ins[2], ins[3], None)
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n_or = add_and_connect(circuit, name+'~or', 'OR2', None, None, outs[0])
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Line(circuit, n_and0, n_or)
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Line(circuit, n_and1, n_or)
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elif n.kind.startswith('AOI22X'):
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n.remove()
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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n_and1 = add_and_connect(circuit, name+'~and1', 'AND2', ins[2], ins[3], None)
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n_nor = add_and_connect(circuit, name+'~nor', 'NOR2', None, None, outs[0])
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Line(circuit, n_and0, n_nor)
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Line(circuit, n_and1, n_nor)
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elif n.kind.startswith('AO221X'):
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n.remove()
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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n_and1 = add_and_connect(circuit, name+'~and1', 'AND2', ins[2], ins[3], None)
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n_or0 = add_and_connect(circuit, name+'~or0', 'OR2', None, None, None)
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n_or1 = add_and_connect(circuit, name+'~or1', 'OR2', None, ins[4], outs[0])
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Line(circuit, n_and0, n_or0)
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Line(circuit, n_and1, n_or0)
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Line(circuit, n_or0, n_or1)
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elif n.kind.startswith('AOI221X'):
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n.remove()
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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n_and1 = add_and_connect(circuit, name+'~and1', 'AND2', ins[2], ins[3], None)
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n_or = add_and_connect(circuit, name+'~or', 'OR2', None, None, None)
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n_nor = add_and_connect(circuit, name+'~nor', 'NOR2', None, ins[4], outs[0])
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Line(circuit, n_and0, n_or)
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Line(circuit, n_and1, n_or)
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Line(circuit, n_or, n_nor)
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elif n.kind.startswith('OA221X'):
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n.remove()
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n_or0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n_or1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', None, None, None)
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n_and1 = add_and_connect(circuit, name+'~and1', 'AND2', None, ins[4], outs[0])
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Line(circuit, n_or0, n_and0)
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Line(circuit, n_or1, n_and0)
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Line(circuit, n_and0, n_and1)
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elif n.kind.startswith('OAI221X'):
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n.remove()
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n_or0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n_or1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', None, None, None)
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n_nand1 = add_and_connect(circuit, name+'~nand1', 'NAND2', None, ins[4], outs[0])
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Line(circuit, n_or0, n_and0)
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Line(circuit, n_or1, n_and0)
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Line(circuit, n_and0, n_nand1)
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elif n.kind.startswith('AO222X'):
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n.remove()
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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n_and1 = add_and_connect(circuit, name+'~and1', 'AND2', ins[2], ins[3], None)
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n_and2 = add_and_connect(circuit, name+'~and2', 'AND2', ins[4], ins[5], None)
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n_or0 = add_and_connect(circuit, name+'~or0', 'OR2', None, None, None)
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n_or1 = add_and_connect(circuit, name+'~or1', 'OR2', None, None, outs[0])
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Line(circuit, n_and0, n_or0)
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Line(circuit, n_and1, n_or0)
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Line(circuit, n_and2, n_or1)
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Line(circuit, n_or0, n_or1)
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elif n.kind.startswith('AOI222X'):
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n.remove()
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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n_and1 = add_and_connect(circuit, name+'~and1', 'AND2', ins[2], ins[3], None)
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n_and2 = add_and_connect(circuit, name+'~and2', 'AND2', ins[4], ins[5], None)
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n_or0 = add_and_connect(circuit, name+'~or0', 'OR2', None, None, None)
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n_nor1 = add_and_connect(circuit, name+'~nor1', 'NOR2', None, None, outs[0])
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Line(circuit, n_and0, n_or0)
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Line(circuit, n_and1, n_or0)
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Line(circuit, n_and2, n_nor1)
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Line(circuit, n_or0, n_nor1)
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elif n.kind.startswith('OA222X'):
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n.remove()
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n_or0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n_or1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
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n_or2 = add_and_connect(circuit, name+'~or2', 'OR2', ins[4], ins[5], None)
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', None, None, None)
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n_and1 = add_and_connect(circuit, name+'~and1', 'AND2', None, None, outs[0])
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Line(circuit, n_or0, n_and0)
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Line(circuit, n_or1, n_and0)
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Line(circuit, n_or2, n_and1)
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Line(circuit, n_and0, n_and1)
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elif n.kind.startswith('OAI222X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
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n2 = add_and_connect(circuit, name+'~or2', 'OR2', ins[4], ins[5], None)
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n3 = add_and_connect(circuit, name+'~and0', 'AND2', None, None, None)
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n4 = add_and_connect(circuit, name+'~nand1', 'NAND2', None, None, outs[0])
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Line(circuit, n0, n3)
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Line(circuit, n1, n3)
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Line(circuit, n2, n4)
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Line(circuit, n3, n4)
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elif n.kind.startswith('AND3X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~and1', 'AND2', None, ins[2], outs[0])
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Line(circuit, n0, n1)
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elif n.kind.startswith('OR3X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~or1', 'OR2', None, ins[2], outs[0])
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Line(circuit, n0, n1)
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elif n.kind.startswith('XOR3X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~xor0', 'XOR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~xor1', 'XOR2', None, ins[2], outs[0])
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Line(circuit, n0, n1)
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elif n.kind.startswith('NAND3X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~and', 'AND2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~nand', 'NAND2', None, ins[2], outs[0])
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Line(circuit, n0, n1)
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elif n.kind.startswith('NOR3X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~or', 'OR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~nor', 'NOR2', None, ins[2], outs[0])
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Line(circuit, n0, n1)
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elif n.kind.startswith('XNOR3X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~xor', 'XOR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~xnor', 'XNOR2', None, ins[2], outs[0])
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Line(circuit, n0, n1)
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elif n.kind.startswith('AND4X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~and1', 'AND2', ins[2], ins[3], None)
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n2 = add_and_connect(circuit, name+'~and2', 'AND2', None, None, outs[0])
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Line(circuit, n0, n2)
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Line(circuit, n1, n2)
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elif n.kind.startswith('OR4X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
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n2 = add_and_connect(circuit, name+'~or2', 'OR2', None, None, outs[0])
|
|
||||||
Line(circuit, n0, n2)
|
|
||||||
Line(circuit, n1, n2)
|
|
||||||
elif n.kind.startswith('NAND4X'):
|
|
||||||
n.remove()
|
|
||||||
n0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
|
|
||||||
n1 = add_and_connect(circuit, name+'~and1', 'AND2', ins[2], ins[3], None)
|
|
||||||
n2 = add_and_connect(circuit, name+'~nand2', 'NAND2', None, None, outs[0])
|
|
||||||
Line(circuit, n0, n2)
|
|
||||||
Line(circuit, n1, n2)
|
|
||||||
elif n.kind.startswith('NOR4X'):
|
|
||||||
n.remove()
|
|
||||||
n0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
|
|
||||||
n1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
|
|
||||||
n2 = add_and_connect(circuit, name+'~nor2', 'NOR2', None, None, outs[0])
|
|
||||||
Line(circuit, n0, n2)
|
|
||||||
Line(circuit, n1, n2)
|
|
||||||
elif n.kind.startswith('FADDX'):
|
|
||||||
n.remove()
|
|
||||||
# forks for fan-outs
|
|
||||||
f_a = add_and_connect(circuit, name + '~fork0', '__fork__', ins[0])
|
|
||||||
f_b = add_and_connect(circuit, name + '~fork1', '__fork__', ins[1])
|
|
||||||
f_ci = add_and_connect(circuit, name + '~fork2', '__fork__', ins[2])
|
|
||||||
f_ab = Node(circuit, name + '~fork3')
|
|
||||||
# sum-block
|
|
||||||
n_xor0 = Node(circuit, name + '~xor0', 'XOR2')
|
|
||||||
Line(circuit, f_a, n_xor0)
|
|
||||||
Line(circuit, f_b, n_xor0)
|
|
||||||
Line(circuit, n_xor0, f_ab)
|
|
||||||
if len(outs) > 0 and outs[0] is not None:
|
|
||||||
n_xor1 = add_and_connect(circuit, name + '~xor1', 'XOR2', None, None, outs[0])
|
|
||||||
Line(circuit, f_ab, n_xor1)
|
|
||||||
Line(circuit, f_ci, n_xor1)
|
|
||||||
# carry-block
|
|
||||||
if len(outs) > 1 and outs[1] is not None:
|
|
||||||
n_and0 = Node(circuit, name + '~and0', 'AND2')
|
|
||||||
Line(circuit, f_ab, n_and0)
|
|
||||||
Line(circuit, f_ci, n_and0)
|
|
||||||
n_and1 = Node(circuit, name + '~and1', 'AND2')
|
|
||||||
Line(circuit, f_a, n_and1)
|
|
||||||
Line(circuit, f_b, n_and1)
|
|
||||||
n_or = add_and_connect(circuit, name + '~or0', 'OR2', None, None, outs[1])
|
|
||||||
Line(circuit, n_and0, n_or)
|
|
||||||
Line(circuit, n_and1, n_or)
|
|
||||||
elif n.kind.startswith('HADDX'):
|
|
||||||
n.remove()
|
|
||||||
# forks for fan-outs
|
|
||||||
f_a = add_and_connect(circuit, name + '~fork0', '__fork__', ins[0])
|
|
||||||
f_b = add_and_connect(circuit, name + '~fork1', '__fork__', ins[1])
|
|
||||||
n_xor0 = add_and_connect(circuit, name + '~xor0', 'XOR2', None, None, outs[1])
|
|
||||||
Line(circuit, f_a, n_xor0)
|
|
||||||
Line(circuit, f_b, n_xor0)
|
|
||||||
n_and0 = add_and_connect(circuit, name + '~and0', 'AND2', None, None, outs[0])
|
|
||||||
Line(circuit, f_a, n_and0)
|
|
||||||
Line(circuit, f_b, n_and0)
|
|
||||||
elif n.kind.startswith('MUX21X'):
|
|
||||||
n.remove()
|
|
||||||
f_s = add_and_connect(circuit, name + '~fork0', '__fork__', ins[2])
|
|
||||||
n_not = Node(circuit, name + '~not', 'INV')
|
|
||||||
Line(circuit, f_s, n_not)
|
|
||||||
n_and0 = add_and_connect(circuit, name + '~and0', 'AND2', ins[0])
|
|
||||||
n_and1 = add_and_connect(circuit, name + '~and1', 'AND2', ins[1])
|
|
||||||
n_or0 = add_and_connect(circuit, name + '~or0', 'OR2', None, None, outs[0])
|
|
||||||
Line(circuit, n_not, n_and0)
|
|
||||||
Line(circuit, f_s, n_and1)
|
|
||||||
Line(circuit, n_and0, n_or0)
|
|
||||||
Line(circuit, n_and1, n_or0)
|
|
||||||
elif n.kind.startswith('DFFSSR'):
|
|
||||||
n.kind = 'DFFX1'
|
n.kind = 'DFFX1'
|
||||||
n_and0 = add_and_connect(circuit, name + '~and0', 'AND2', ins[0], ins[2], None)
|
n_and0 = add_and_connect(circuit, n.name + '~and0', 'AND2', n.ins[0], n.ins[2], None)
|
||||||
Line(circuit, n_and0, (n, 0))
|
Line(circuit, n_and0, (n, 0))
|
||||||
|
else:
|
||||||
|
for k, v in tmap.items():
|
||||||
|
if n.kind.startswith(k):
|
||||||
|
circuit.substitute(n, v)
|
||||||
@@ -48,9 +48,13 @@ class VerilogTransformer(Transformer):
|
|||||||
|
|
||||||
@staticmethod
|
@staticmethod
|
||||||
def instantiation(args):
|
def instantiation(args):
|
||||||
return Instantiation(args[0], args[1],
|
pinmap = {}
|
||||||
dict((pin.children[0],
|
for idx, pin in enumerate(args[2:]):
|
||||||
pin.children[1]) for pin in args[2:] if len(pin.children) > 1))
|
if len(pin.children) > 1:
|
||||||
|
pinmap[pin.children[0]] = pin.children[1]
|
||||||
|
else:
|
||||||
|
pinmap[idx] = pin.children[0]
|
||||||
|
return Instantiation(args[0], args[1], pinmap)
|
||||||
|
|
||||||
def range(self, args):
|
def range(self, args):
|
||||||
left = int(args[0].value)
|
left = int(args[0].value)
|
||||||
@@ -186,7 +190,7 @@ GRAMMAR = r"""
|
|||||||
wire: "wire" range? _namelist ";"
|
wire: "wire" range? _namelist ";"
|
||||||
assign: "assign" sigsel "=" sigsel ";"
|
assign: "assign" sigsel "=" sigsel ";"
|
||||||
instantiation: name name "(" [ pin ( "," pin )* ] ")" ";"
|
instantiation: name name "(" [ pin ( "," pin )* ] ")" ";"
|
||||||
pin: "." name "(" sigsel? ")"
|
pin: ("." name "(" sigsel? ")" ) | sigsel
|
||||||
range: "[" /[0-9]+/ (":" /[0-9]+/)? "]"
|
range: "[" /[0-9]+/ (":" /[0-9]+/)? "]"
|
||||||
sigsel: name range? | concat
|
sigsel: name range? | concat
|
||||||
concat: "{" sigsel ( "," sigsel )* "}"
|
concat: "{" sigsel ( "," sigsel )* "}"
|
||||||
|
|||||||
Reference in new issue
Block a user