diff --git a/tests/test_verilog.py b/tests/test_verilog.py
index 816c12b..77f9de0 100644
--- a/tests/test_verilog.py
+++ b/tests/test_verilog.py
@@ -9,7 +9,7 @@ def test_b01(mydir):
 
     assert len(c.nodes) == 139
     assert len(c.lines) == 203
-    stats = c.stats
+    stats = c.stats(SAED90)
     assert stats['input'] == 6
     assert stats['output'] == 3
     assert stats['__seq__'] == 5
@@ -19,7 +19,7 @@ def test_b15(mydir):
     c = verilog.load(mydir / 'b15_4ig.v.gz', tlib=SAED32)
     assert len(c.nodes) == 12067
     assert len(c.lines) == 20731
-    stats = c.stats
+    stats = c.stats(SAED32)
     assert stats['input'] == 40
     assert stats['output'] == 71
     assert stats['__seq__'] == 417
@@ -29,7 +29,7 @@ def test_gates(mydir):
     c = verilog.load(mydir / 'gates.v', tlib=NANGATE45)
     assert len(c.nodes) == 18
     assert len(c.lines) == 21
-    stats = c.stats
+    stats = c.stats(NANGATE45)
     assert stats['input'] == 3
     assert stats['output'] == 4
     assert stats['__seq__'] == 0
@@ -39,7 +39,7 @@ def test_halton2(mydir):
     c = verilog.load(mydir / 'rng_haltonBase2.synth_yosys.v', tlib=SAED90)
     assert len(c.nodes) == 146
     assert len(c.lines) == 210
-    stats = c.stats
+    stats = c.stats(SAED90)
     assert stats['input'] == 2
     assert stats['output'] == 12
     assert stats['__seq__'] == 12
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