for release 0.0.5
* Techlib: fix NanGate variants * Circuit: more visitor and manipulator utilities * mv_transition: produce stable values when arguments are UNASSIGNED * Verilog: better assign processing * STIL parsing improvements * SDF: conditional parsing (semantics ignored for now), better interconnect annotation, more robust name matching * sim: use ALAP topo-sort * logic_sim: improved fault injection, faster 6V sim * wave_sim: use correct thresholds for pulse filtering, partial delta-sim support, per-sim delay factor * log: fix limiter
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@@ -13,8 +13,44 @@ def b15_2ig_circuit(mydir):
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from kyupy.techlib import SAED32
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return verilog.load(mydir / 'b15_2ig.v.gz', branchforks=True, tlib=SAED32)
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@pytest.fixture(scope='session')
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def b15_2ig_circuit_resolved(b15_2ig_circuit):
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from kyupy.techlib import SAED32
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cr = b15_2ig_circuit.copy()
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cr.resolve_tlib_cells(SAED32)
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return cr
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@pytest.fixture(scope='session')
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def b15_4ig_circuit(mydir):
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from kyupy import verilog
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from kyupy.techlib import SAED32
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return verilog.load(mydir / 'b15_4ig.v.gz', branchforks=True, tlib=SAED32)
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@pytest.fixture(scope='session')
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def b15_4ig_circuit_resolved(b15_4ig_circuit):
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from kyupy.techlib import SAED32
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cr = b15_4ig_circuit.copy()
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cr.resolve_tlib_cells(SAED32)
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return cr
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@pytest.fixture(scope='session')
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def b15_2ig_delays(mydir, b15_2ig_circuit):
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from kyupy import sdf
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from kyupy.techlib import SAED32
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return sdf.load(mydir / 'b15_2ig.sdf.gz').iopaths(b15_2ig_circuit, tlib=SAED32)[1:2]
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@pytest.fixture(scope='session')
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def b15_2ig_sa_nf_test_resp(mydir, b15_2ig_circuit_resolved):
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from kyupy import stil
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s = stil.load(mydir / 'b15_2ig.sa_nf.stil.gz')
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tests = s.tests(b15_2ig_circuit_resolved)[:,1:]
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resp = s.responses(b15_2ig_circuit_resolved)[:,1:]
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return (tests, resp)
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@pytest.fixture(scope='session')
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def b15_4ig_sa_rf_test_resp(mydir, b15_4ig_circuit_resolved):
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from kyupy import stil
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s = stil.load(mydir / 'b15_4ig.sa_rf.stil.gz')
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tests = s.tests(b15_4ig_circuit_resolved)[:,1:]
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resp = s.responses(b15_4ig_circuit_resolved)[:,1:]
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return (tests, resp)
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+33
-6
@@ -7,22 +7,49 @@
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(TEMPERATURE 25.00:25.00:25.00)
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(TIMESCALE 1ns)
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(CELL
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(CELLTYPE "NAND2X1")
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(CELLTYPE "NAND2_X1")
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(INSTANCE nandgate)
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(DELAY
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(ABSOLUTE
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(IOPATH IN1 QN (0.099:0.103:0.103) (0.122:0.127:0.127))
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(IOPATH IN2 QN (0.083:0.086:0.086) (0.100:0.104:0.104))
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(IOPATH A1 ZN (0.099:0.103:0.103) (0.122:0.127:0.127))
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(IOPATH A2 ZN (0.083:0.086:0.086) (0.100:0.104:0.104))
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)
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)
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)
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(CELL
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(CELLTYPE "AND2X1")
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(CELLTYPE "AND2_X1")
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(INSTANCE andgate)
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(DELAY
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(ABSOLUTE
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(IOPATH IN1 Q (0.367:0.378:0.378) (0.351:0.377:0.377))
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(IOPATH IN2 Q (0.366:0.375:0.375) (0.359:0.370:0.370))
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(IOPATH A1 ZN (0.367:0.378:0.378) (0.351:0.377:0.377))
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(IOPATH A2 ZN (0.366:0.375:0.375) (0.359:0.370:0.370))
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)
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)
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)
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(CELL
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(CELLTYPE "OAI21_X1")
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(INSTANCE oai21gate)
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(DELAY
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(ABSOLUTE
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(IOPATH B1 ZN (0.000:0.025:0.025) (0.000:0.013:0.013))
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(IOPATH B2 ZN (0.000:0.030:0.030) (0.000:0.016:0.016))
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( COND (B1 == 1'b0) && (B2 == 1'b1) (IOPATH A ZN (0.000:0.018:0.018)))
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(COND (B1 == 1'b1) && (B2 == 1'b0) (IOPATH A ZN (0.000:0.018:0.018) (0.000:0.016:0.016)))
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(COND (B1 == 1'b1) && (B2 == 1'b1) (IOPATH A ZN (0.000:0.019:0.019) (0.000:0.014:0.014)))
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)
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)
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)
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(CELL
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(CELLTYPE "MUX2_X1")
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(INSTANCE mux2gate)
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(DELAY
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(ABSOLUTE
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(COND (B == 1'b0) && (S == 1'b0) (IOPATH A Z (0.000:0.037:0.037) (0.000:0.058:0.058)))
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(COND (B == 1'b1) && (S == 1'b0) (IOPATH A Z (0.000:0.037:0.037) (0.000:0.058:0.058)))
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(COND (A == 1'b0) && (S == 1'b1) (IOPATH B Z (0.000:0.035:0.035) (0.000:0.056:0.056)))
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(COND (A == 1'b1) && (S == 1'b1) (IOPATH B Z (0.000:0.035:0.035) (0.000:0.056:0.056)))
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(COND (A == 1'b0) && (B == 1'b1) (IOPATH S Z (0.000:0.047:0.047) (0.000:0.073:0.073)))
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(COND (A == 1'b1) && (B == 1'b0) (IOPATH S Z (0.000:0.072:0.072) (0.000:0.064:0.064)))
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)
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)
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)
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+8
-4
@@ -1,11 +1,15 @@
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module gates (a, b, o0, o1 );
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module gates (a, b, c, o0, o1, o2, o3 );
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input a;
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input b;
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input c;
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output o0;
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output o1;
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output o2;
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output o3;
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AND2X1 andgate (.IN1 ( a ) , .IN2 ( b ) , .Q ( o0 ) ) ;
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NAND2X1 nandgate (.IN1 ( a ) , .IN2 ( b ) , .QN ( o1 ) ) ;
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AND2_X1 andgate (.A1 ( a ) , .A2 ( b ) , .ZN ( o0 ) ) ;
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NAND2_X1 nandgate (.A1 ( a ) , .A2 ( b ) , .ZN ( o1 ) ) ;
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OAI21_X1 oai21gate (.B1(a), .B2(b), .A(c), .ZN(o2) ) ;
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MUX2_X1 mux2gate (.A(a), .B(b), .S(c), .Z(o3)) ;
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endmodule
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+22
-1
@@ -1,9 +1,30 @@
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import pickle
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from kyupy.circuit import Circuit, Node, Line
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from kyupy.circuit import GrowingList, Circuit, Node, Line
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from kyupy import verilog, bench
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from kyupy.techlib import SAED32
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def test_growing_list():
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gl = GrowingList()
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assert gl.free_idx == 0
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gl[0] = 1
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assert gl.free_idx == 1
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gl[2] = 1
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assert gl.free_idx == 1
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gl[0] = None
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assert gl.free_idx == 0
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gl[0] = 1
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assert gl.free_idx == 1
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gl[1] = 1
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assert gl.free_idx == 3
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gl.append(1)
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assert gl.free_idx == 4
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gl[2] = None
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assert gl.free_idx == 2
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gl[2] = 1
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gl[1] = None
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assert gl.free_idx == 1
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def test_lines():
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c = Circuit()
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n1 = Node(c, 'n1')
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+86
-1
@@ -1,6 +1,6 @@
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import numpy as np
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from kyupy.logic_sim import LogicSim
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from kyupy.logic_sim import LogicSim, LogicSim6V
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from kyupy import bench, logic, sim
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from kyupy.logic import mvarray, bparray, bp_to_mv, mv_to_bp
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@@ -94,6 +94,30 @@ def test_4v():
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'--0XX', '--X1X', '--XXX', '--XXX'))
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def test_6v():
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c = bench.parse('input(x, y) output(a, o, n, xo, no) a=AND2(x,y) o=OR2(x,y) n=INV1(x) xo=XOR2(x,y) no=NOR2(x,y)')
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s = LogicSim6V(c, 36)
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assert s.s_len == 7
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mva = mvarray(
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'0000101', '0101110', '0R0R1RF', '0F0F1FR', '0P0P1PN', '0N0N1NP',
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'1001010', '1111000', '1RR10F0', '1FF10R0', '1PP10N0', '1NN10P0',
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'R00RFRF', 'R1R1FF0', 'RRRRFPF', 'RFPNFNP', 'RPPRFRF', 'RNRNFFP',
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'F00FRFR', 'F1F1RR0', 'FRPNRNP', 'FFFFRPR', 'FPPFRFR', 'FNFNRRP',
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'P00PNPN', 'P1P1NN0', 'PRPRNRF', 'PFPFNFR', 'PPPPNPN', 'PNPNNNP',
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'N00NPNP', 'N1N1PP0', 'NRRNPFP', 'NFFNPRP', 'NPPNPNP', 'NNNNPPP')
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tests = np.copy(mva)
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tests[2:] = logic.ZERO
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s.s[0] = tests
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s.s_to_c()
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s.c_prop()
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s.c_to_s()
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resp = s.s[1].copy()
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exp_resp = np.copy(mva)
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exp_resp[:2] = logic.ZERO
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np.testing.assert_allclose(resp, exp_resp)
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def test_8v():
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c = bench.parse('input(x, y) output(a, o, n, xo) a=and(x,y) o=or(x,y) n=not(x) xo=xor(x,y)')
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s = LogicSim(c, 64, m=8)
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@@ -173,3 +197,64 @@ def test_b01(mydir):
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s.c_prop()
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s.c_to_s()
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bp_to_mv(s.s[1])
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def sim_and_compare(c, test_resp, m=8):
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tests, resp = test_resp
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lsim = LogicSim(c, m=m, sims=tests.shape[1])
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lsim.s[0] = logic.mv_to_bp(tests)
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lsim.s_to_c()
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lsim.c_prop()
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lsim.c_to_s()
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resp_sim = logic.bp_to_mv(lsim.s[1])[:,:tests.shape[1]]
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idxs, pats = np.nonzero(((resp == logic.ONE) & (resp_sim != logic.ONE)) | ((resp == logic.ZERO) & (resp_sim != logic.ZERO)))
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for i, (idx, pat) in enumerate(zip(idxs, pats)):
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if i >= 10:
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print(f'...')
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break
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print(f'mismatch pattern:{pat} ppio:{idx} exp:{logic.mv_str(resp[idx,pat])} act:{logic.mv_str(resp_sim[idx,pat])}')
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assert len(idxs) == 0
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def sim_and_compare_6v(c, test_resp):
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tests, resp = test_resp
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lsim = LogicSim6V(c, sims=tests.shape[1])
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lsim.s[0] = tests
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lsim.s_to_c()
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lsim.c_prop()
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lsim.c_to_s()
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resp_sim = lsim.s[1]
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idxs, pats = np.nonzero(((resp == logic.ONE) & (resp_sim != logic.ONE)) | ((resp == logic.ZERO) & (resp_sim != logic.ZERO)))
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for i, (idx, pat) in enumerate(zip(idxs, pats)):
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if i >= 10:
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print(f'...')
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break
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print(f'mismatch pattern:{pat} ppio:{idx} exp:{logic.mv_str(resp[idx,pat])} act:{logic.mv_str(resp_sim[idx,pat])}')
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assert len(idxs) == 0
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def test_b15_2ig_sa_2v(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp):
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sim_and_compare(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp, m=2)
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def test_b15_2ig_sa_4v(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp):
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sim_and_compare(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp, m=4)
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def test_b15_2ig_sa_6v(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp):
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sim_and_compare_6v(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp)
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def test_b15_2ig_sa_8v(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp):
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sim_and_compare(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp, m=8)
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def test_b15_4ig_sa_2v(b15_4ig_circuit_resolved, b15_4ig_sa_rf_test_resp):
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sim_and_compare(b15_4ig_circuit_resolved, b15_4ig_sa_rf_test_resp, m=2)
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def test_b15_4ig_sa_4v(b15_4ig_circuit_resolved, b15_4ig_sa_rf_test_resp):
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sim_and_compare(b15_4ig_circuit_resolved, b15_4ig_sa_rf_test_resp, m=4)
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def test_b15_4ig_sa_8v(b15_4ig_circuit_resolved, b15_4ig_sa_rf_test_resp):
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sim_and_compare(b15_4ig_circuit_resolved, b15_4ig_sa_rf_test_resp, m=8)
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+3
-3
@@ -2,7 +2,7 @@ import numpy as np
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from kyupy import sdf, verilog, bench
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from kyupy.wave_sim import WaveSim, TMAX, TMIN
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from kyupy.techlib import SAED32, SAED90
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from kyupy.techlib import SAED32, NANGATE45
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def test_parse():
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test = '''
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@@ -80,9 +80,9 @@ def test_b15(mydir):
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def test_gates(mydir):
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c = verilog.load(mydir / 'gates.v', tlib=SAED90)
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c = verilog.load(mydir / 'gates.v', tlib=NANGATE45)
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df = sdf.load(mydir / 'gates.sdf')
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lt = df.iopaths(c, tlib=SAED90)[1]
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lt = df.iopaths(c, tlib=NANGATE45)[1]
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nand_a = c.cells['nandgate'].ins[0]
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nand_b = c.cells['nandgate'].ins[1]
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and_a = c.cells['andgate'].ins[0]
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@@ -1,5 +1,5 @@
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from kyupy import verilog
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from kyupy.techlib import SAED90, SAED32
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from kyupy.techlib import SAED90, SAED32, NANGATE45
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def test_b01(mydir):
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with open(mydir / 'b01.v', 'r') as f:
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@@ -26,12 +26,12 @@ def test_b15(mydir):
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def test_gates(mydir):
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c = verilog.load(mydir / 'gates.v', tlib=SAED90)
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assert len(c.nodes) == 10
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assert len(c.lines) == 10
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c = verilog.load(mydir / 'gates.v', tlib=NANGATE45)
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assert len(c.nodes) == 18
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assert len(c.lines) == 21
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stats = c.stats
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assert stats['input'] == 2
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assert stats['output'] == 2
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assert stats['input'] == 3
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assert stats['output'] == 4
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assert stats['__seq__'] == 0
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+47
-13
@@ -5,22 +5,56 @@ from kyupy.logic_sim import LogicSim
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from kyupy import logic, bench, sim
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from kyupy.logic import mvarray
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def test_xnor2_delays():
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op = (sim.XNOR2, 2, 0, 1, 3, 3, -1, 0, 0)
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#op = (0b0111, 4, 0, 1)
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c = np.full((4*16, 1), TMAX, dtype=np.float32) # 4 waveforms of capacity 16
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c_locs = np.zeros((4,), dtype='int')
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c_caps = np.zeros((4,), dtype='int')
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ebuf = np.zeros((4, 1, 2), dtype=np.int32)
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for i in range(4): c_locs[i], c_caps[i] = i*16, 16 # 1:1 mapping
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delays = np.zeros((1, 4, 2, 2))
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delays[0, 0, 0, 0] = 0.031 # A rise -> Z rise
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delays[0, 0, 0, 1] = 0.027 # A rise -> Z fall
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delays[0, 0, 1, 0] = 0.033 # A fall -> Z rise
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delays[0, 0, 1, 1] = 0.037 # A fall -> Z fall
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delays[0, 1, 0, 0] = 0.032 # B rise -> Z rise
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delays[0, 1, 0, 1] = 0.030 # B rise -> Z fall
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delays[0, 1, 1, 0] = 0.038 # B fall -> Z rise
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delays[0, 1, 1, 1] = 0.036 # B fall -> Z fall
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simctl_int = np.asarray([0], dtype=np.int32)
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def wave_assert(inputs, output):
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for i, a in zip(inputs, c.reshape(-1,16)): a[:len(i)] = i
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wave_eval_cpu(op, c, c_locs, c_caps, ebuf, 0, delays, simctl_int, 0, 0)
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for i, v in enumerate(output): np.testing.assert_allclose(c.reshape(-1,16)[2,i], v)
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wave_assert([[TMIN,TMAX],[TMIN,TMAX]], [TMIN,TMAX]) # XNOR(1,1) => 1
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wave_assert([[TMAX,TMAX],[TMIN,TMAX]], [TMAX]) # XNOR(0,1) => 0
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# using Afall/Zfall for pulse length, bug: was using Arise/Zfall
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#wave_assert([[0.07, 0.10, TMAX], [0.0, TMAX]], [TMIN, 0.03, 0.101, 0.137, TMAX])
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wave_assert([[0.07, 0.10, TMAX], [0.0, TMAX]], [TMIN, 0.03, TMAX])
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wave_assert([[0.06, 0.10, TMAX], [0.0, TMAX]], [TMIN, 0.03, 0.091, 0.137, TMAX])
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def test_nand_delays():
|
||||
op = (sim.NAND4, 4, 0, 1, 2, 3, -1, 0, 0)
|
||||
#op = (0b0111, 4, 0, 1)
|
||||
c = np.full((5*16, 1), TMAX) # 5 waveforms of capacity 16
|
||||
c = np.full((5*16, 1), TMAX, dtype=np.float32) # 5 waveforms of capacity 16
|
||||
c_locs = np.zeros((5,), dtype='int')
|
||||
c_caps = np.zeros((5,), dtype='int')
|
||||
ebuf = np.zeros((4, 1, 2), dtype=np.int32)
|
||||
|
||||
for i in range(5): c_locs[i], c_caps[i] = i*16, 16 # 1:1 mapping
|
||||
|
||||
# SDF specifies IOPATH delays with respect to output polarity
|
||||
# SDF pulse rejection value is determined by IOPATH causing last transition and polarity of last transition
|
||||
delays = np.zeros((1, 5, 2, 2))
|
||||
delays[0, 0, 0, 0] = 0.1 # A -> Z rise delay
|
||||
delays[0, 0, 0, 1] = 0.2 # A -> Z fall delay
|
||||
delays[0, 0, 1, 0] = 0.1 # A -> Z negative pulse limit (terminate in rising Z)
|
||||
delays[0, 0, 1, 1] = 0.2 # A -> Z positive pulse limit
|
||||
delays[0, 0, 0, 0] = 0.1 # A rise -> Z rise
|
||||
delays[0, 0, 0, 1] = 0.2 # A rise -> Z fall
|
||||
delays[0, 0, 1, 0] = 0.1 # A fall -> Z rise
|
||||
delays[0, 0, 1, 1] = 0.2 # A fall -> Z fall
|
||||
delays[0, 1, :, 0] = 0.3 # as above for B -> Z
|
||||
delays[0, 1, :, 1] = 0.4
|
||||
delays[0, 2, :, 0] = 0.5 # as above for C -> Z
|
||||
@@ -32,7 +66,7 @@ def test_nand_delays():
|
||||
|
||||
def wave_assert(inputs, output):
|
||||
for i, a in zip(inputs, c.reshape(-1,16)): a[:len(i)] = i
|
||||
wave_eval_cpu(op, c, c_locs, c_caps, 0, delays, simctl_int)
|
||||
wave_eval_cpu(op, c, c_locs, c_caps, ebuf, 0, delays, simctl_int, 0, 0)
|
||||
for i, v in enumerate(output): np.testing.assert_allclose(c.reshape(-1,16)[4,i], v)
|
||||
|
||||
wave_assert([[TMAX,TMAX],[TMAX,TMAX],[TMIN,TMAX],[TMIN,TMAX]], [TMIN,TMAX]) # NAND(0,0,1,1) => 1
|
||||
@@ -145,7 +179,7 @@ def compare_to_logic_sim(wsim: WaveSim):
|
||||
lsim.s_to_c()
|
||||
lsim.c_prop()
|
||||
lsim.c_to_s()
|
||||
exp = logic.bp_to_mv(lsim.s[1])
|
||||
exp = logic.bp_to_mv(lsim.s[1])[:,:tests.shape[-1]]
|
||||
|
||||
resp[resp == logic.PPULSE] = logic.ZERO
|
||||
resp[resp == logic.NPULSE] = logic.ONE
|
||||
@@ -156,13 +190,13 @@ def compare_to_logic_sim(wsim: WaveSim):
|
||||
np.testing.assert_allclose(resp, exp)
|
||||
|
||||
|
||||
def test_b15(b15_2ig_circuit, b15_2ig_delays):
|
||||
compare_to_logic_sim(WaveSim(b15_2ig_circuit, b15_2ig_delays, 8))
|
||||
def test_b15(b15_2ig_circuit_resolved, b15_2ig_delays):
|
||||
compare_to_logic_sim(WaveSim(b15_2ig_circuit_resolved, b15_2ig_delays, 8))
|
||||
|
||||
|
||||
def test_b15_strip_forks(b15_2ig_circuit, b15_2ig_delays):
|
||||
compare_to_logic_sim(WaveSim(b15_2ig_circuit, b15_2ig_delays, 8, strip_forks=True))
|
||||
def test_b15_strip_forks(b15_2ig_circuit_resolved, b15_2ig_delays):
|
||||
compare_to_logic_sim(WaveSim(b15_2ig_circuit_resolved, b15_2ig_delays, 8, strip_forks=True))
|
||||
|
||||
|
||||
def test_b15_cuda(b15_2ig_circuit, b15_2ig_delays):
|
||||
compare_to_logic_sim(WaveSimCuda(b15_2ig_circuit, b15_2ig_delays, 8, strip_forks=True))
|
||||
def test_b15_cuda(b15_2ig_circuit_resolved, b15_2ig_delays):
|
||||
compare_to_logic_sim(WaveSimCuda(b15_2ig_circuit_resolved, b15_2ig_delays, 8, strip_forks=True))
|
||||
Reference in new issue
Block a user