line use and diff
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+9
-1
@@ -187,7 +187,6 @@ class SimOps:
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levels = []
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ppio2idx = dict((n, i) for i, n in enumerate(circuit.s_nodes))
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pis = set([n for n in circuit.s_nodes if len(n.ins) == 0])
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ppos = set([n for n in circuit.s_nodes if len(n.ins) > 0])
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readers = np.array([1 if l.reader in ppos else len(l.reader.outs) for l in circuit.lines], dtype=np.int32) # for ref-counting forks
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@@ -311,6 +310,15 @@ class SimOps:
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if len(n.ins) > 0:
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self.c_locs[self.ppo_offset + i], self.c_caps[self.ppo_offset + i] = self.c_locs[n.ins[0]], self.c_caps[n.ins[0]]
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# line use information
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self.line_use_start = np.full(self.c_locs_len, -1, dtype=np.int32)
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self.line_use_stop = np.full(self.c_locs_len, len(self.levels), dtype=np.int32)
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for i, lv in enumerate(self.levels):
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for op in lv:
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self.line_use_start[op[1]] = i
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for x in [2, 3, 4, 5]:
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self.line_use_stop[op[x]] = i
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self.c_len = h.max_size
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d = defaultdict(int)
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+109
-14
@@ -13,10 +13,11 @@ Two simulators are available: :py:class:`WaveSim` runs on the CPU, and the deriv
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"""
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import math
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from collections import defaultdict
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import numpy as np
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from . import numba, cuda, sim, cdiv, eng
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from . import log, numba, cuda, sim, cdiv, eng
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TMAX = np.float32(2 ** 127)
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@@ -59,8 +60,8 @@ class WaveSim(sim.SimOps):
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self.delays = np.zeros((len(delays), self.c_locs_len, 2, 2), dtype=delays.dtype)
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self.delays[:, :delays.shape[1]] = delays
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self.c = np.zeros((self.c_len, sims), dtype=np.float32) + TMAX
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self.s = np.zeros((11, self.s_len, sims), dtype=np.float32)
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self.c = np.full((self.c_len, self.sims), TMAX, dtype=np.float32)
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self.s = np.zeros((11, self.s_len, self.sims), dtype=np.float32)
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"""Information about the logic values and transitions around the sequential elements (flip-flops) and ports.
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The first 3 values are read by :py:func:`s_to_c`.
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@@ -98,7 +99,26 @@ class WaveSim(sim.SimOps):
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self.simctl_int[0] = range(sims) # unique seed for each sim by default, zero this to pick same delays for all sims.
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self.simctl_int[1] = 2 # random picking by default.
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self.nbytes = sum([a.nbytes for a in (self.c, self.s, self.c_locs, self.c_caps, self.ops, self.simctl_int)])
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# flat array for line use information
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line_use = defaultdict(list)
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for lidx in range(len(self.circuit.lines)):
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if self.line_use_start[lidx] < 0: continue
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if self.line_use_stop[lidx] < 0:
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log.warn(f'line {lidx} never read?')
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for i in range(self.line_use_start[lidx], self.line_use_stop[lidx]):
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line_use[i].append(lidx)
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self.line_use_counts = np.array([len(line_use[i]) for i in range(len(self.levels))], dtype=np.int32)
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self.line_use_offsets = np.zeros_like(self.line_use_counts)
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self.line_use_offsets[1:] = self.line_use_counts.cumsum()[:-1]
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self.line_use = np.hstack([line_use[i] for i in range(len(self.levels))])
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self.h = np.zeros((self.c_locs_len, sims), dtype=np.float32) # hashes of generated waveforms
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self.h_base = np.zeros_like(self.h) # base hashes to compare to
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self.error_counts = np.zeros(self.s_len, dtype=np.uint32) # number of capture errors by PPO
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self.nbytes = sum([a.nbytes for a in (self.c, self.s, self.h, self.c_locs, self.c_caps, self.ops, self.simctl_int)])
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def __repr__(self):
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dev = 'GPU' if hasattr(self.c, 'copy_to_host') else 'CPU'
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@@ -124,7 +144,7 @@ class WaveSim(sim.SimOps):
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"""
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sims = min(sims or self.sims, self.sims)
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for op_start, op_stop in zip(self.level_starts, self.level_stops):
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level_eval_cpu(self.ops, op_start, op_stop, self.c, self.c_locs, self.c_caps, self.abuf, 0, sims, self.delays, self.simctl_int, seed)
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level_eval_cpu(self.ops, op_start, op_stop, self.c, self.c_locs, self.c_caps, self.h, self.abuf, 0, sims, self.delays, self.simctl_int, seed)
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def c_to_s(self, time=TMAX, sd=0.0, seed=1):
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"""Simulates a capture operation at all sequential elements and primary outputs.
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@@ -152,7 +172,7 @@ class WaveSim(sim.SimOps):
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self.s[2, self.ppio_s_locs] = self.s[8, self.ppio_s_locs]
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def _wave_eval(op, cbuf, c_locs, c_caps, sim, delays, simctl_int, seed=0):
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def _wave_eval(op, cbuf, c_locs, c_caps, hbuf, sim, delays, simctl_int, seed):
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overflows = int(0)
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lut = op[0]
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@@ -182,6 +202,8 @@ def _wave_eval(op, cbuf, c_locs, c_caps, sim, delays, simctl_int, seed=0):
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z_mem = c_locs[z_idx]
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z_cap = c_caps[z_idx]
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h = np.float32(0)
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a_cur = int(0)
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b_cur = int(0)
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c_cur = int(0)
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@@ -229,6 +251,7 @@ def _wave_eval(op, cbuf, c_locs, c_caps, sim, delays, simctl_int, seed=0):
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next_t = cbuf[d_mem + d_cur, sim] + delays[d_idx, (d_cur & 1) ^ 1, z_val ^ 1]
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if (z_cur & 1) != ((lut >> inputs) & 1):
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h += h*3 + max(current_t, -10) # hash based on generated transitions before filtering
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# we generate an edge in z_mem, if ...
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if (z_cur == 0 # it is the first edge in z_mem ...
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or next_t < current_t # -OR- the next edge on SAME input is EARLIER (need current edge to filter BOTH in next iteration) ...
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@@ -240,8 +263,8 @@ def _wave_eval(op, cbuf, c_locs, c_caps, sim, delays, simctl_int, seed=0):
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z_cur += 1
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else:
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overflows += 1
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previous_t = cbuf[z_mem + z_cur - 1, sim]
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z_cur -= 1
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previous_t = cbuf[z_mem + z_cur, sim]
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else:
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z_cur -= 1
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previous_t = cbuf[z_mem + z_cur - 1, sim] if z_cur > 0 else TMIN
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@@ -258,6 +281,8 @@ def _wave_eval(op, cbuf, c_locs, c_caps, sim, delays, simctl_int, seed=0):
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# generate or propagate overflow flag
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cbuf[z_mem + z_cur, sim] = TMAX_OVL if overflows > 0 else max(a, b, c, d)
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hbuf[z_idx, sim] = h
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nrise = max(0, (z_cur+1) // 2 - (cbuf[z_mem, sim] == TMIN))
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nfall = z_cur // 2
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@@ -268,11 +293,11 @@ wave_eval_cpu = numba.njit(_wave_eval)
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@numba.njit
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def level_eval_cpu(ops, op_start, op_stop, c, c_locs, c_caps, abuf, sim_start, sim_stop, delays, simctl_int, seed):
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def level_eval_cpu(ops, op_start, op_stop, c, c_locs, c_caps, hbuf, abuf, sim_start, sim_stop, delays, simctl_int, seed):
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for op_idx in range(op_start, op_stop):
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op = ops[op_idx]
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for sim in range(sim_start, sim_stop):
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nrise, nfall = wave_eval_cpu(op, c, c_locs, c_caps, sim, delays, simctl_int[:, sim], seed)
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nrise, nfall = wave_eval_cpu(op, c, c_locs, c_caps, hbuf, sim, delays, simctl_int[:, sim], seed)
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a_loc = op[6]
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a_wr = op[7]
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a_wf = op[8]
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@@ -345,12 +370,18 @@ class WaveSimCuda(WaveSim):
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self.delays = cuda.to_device(self.delays)
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self.simctl_int = cuda.to_device(self.simctl_int)
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self.abuf = cuda.to_device(self.abuf)
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self.h = cuda.to_device(self.h)
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self.h_base = cuda.to_device(self.h_base)
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self.line_use = cuda.to_device(self.line_use)
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self.error_counts = cuda.to_device(self.error_counts)
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self.retval_int = cuda.to_device(np.array([0], dtype=np.int32))
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self._block_dim = (32, 16)
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def __getstate__(self):
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state = self.__dict__.copy()
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state['c'] = np.array(self.c)
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del state['c']
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state['s'] = np.array(self.s)
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state['ops'] = np.array(self.ops)
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state['c_locs'] = np.array(self.c_locs)
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@@ -358,11 +389,16 @@ class WaveSimCuda(WaveSim):
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state['delays'] = np.array(self.delays)
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state['simctl_int'] = np.array(self.simctl_int)
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state['abuf'] = np.array(self.abuf)
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state['h'] = np.array(self.h)
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state['h_base'] = np.array(self.h_base)
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state['line_use'] = np.array(self.line_use)
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state['error_counts'] = np.array(self.error_counts)
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state['retval_int'] = np.array(self.retval_int)
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return state
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def __setstate__(self, state):
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self.__dict__.update(state)
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self.c = cuda.to_device(self.c)
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self.c = cuda.to_device(np.full((self.c_len, self.sims), TMAX, dtype=np.float32))
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self.s = cuda.to_device(self.s)
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self.ops = cuda.to_device(self.ops)
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self.c_locs = cuda.to_device(self.c_locs)
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@@ -370,6 +406,11 @@ class WaveSimCuda(WaveSim):
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self.delays = cuda.to_device(self.delays)
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self.simctl_int = cuda.to_device(self.simctl_int)
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self.abuf = cuda.to_device(self.abuf)
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self.h = cuda.to_device(self.h)
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self.h_base = cuda.to_device(self.h_base)
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self.line_use = cuda.to_device(self.line_use)
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self.error_counts = cuda.to_device(self.error_counts)
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self.retval_int = cuda.to_device(self.retval_int)
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def s_to_c(self):
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grid_dim = self._grid_dim(self.sims, self.s_len)
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@@ -383,10 +424,18 @@ class WaveSimCuda(WaveSim):
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if op_from > op_start: continue
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if op_to is not None and op_to <= op_start: break
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grid_dim = self._grid_dim(sims, op_stop - op_start)
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wave_eval_gpu[grid_dim, self._block_dim](self.ops, op_start, op_stop, self.c, self.c_locs, self.c_caps, self.abuf, int(0),
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wave_eval_gpu[grid_dim, self._block_dim](self.ops, op_start, op_stop, self.c, self.c_locs, self.c_caps, self.h, self.abuf, int(0),
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sims, self.delays, self.simctl_int, seed)
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cuda.synchronize()
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def c_prop_level(self, level, sims=None, seed=1):
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sims = min(sims or self.sims, self.sims)
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op_start = self.level_starts[level]
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op_stop = self.level_stops[level]
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grid_dim = self._grid_dim(sims, op_stop - op_start)
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wave_eval_gpu[grid_dim, self._block_dim](self.ops, op_start, op_stop, self.c, self.c_locs, self.c_caps, self.h, self.abuf, int(0),
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sims, self.delays, self.simctl_int, seed)
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def c_to_s(self, time=TMAX, sd=0.0, seed=1):
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grid_dim = self._grid_dim(self.sims, self.s_len)
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wave_capture_gpu[grid_dim, self._block_dim](self.c, self.s, self.c_locs, self.c_caps, self.ppo_offset,
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@@ -396,6 +445,52 @@ class WaveSimCuda(WaveSim):
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grid_dim = self._grid_dim(self.sims, self.s_len)
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ppo_to_ppi_gpu[grid_dim, self._block_dim](self.s, self.c_locs, time, self.ppi_offset, self.ppo_offset)
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def set_base_hashes(self):
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nitems = self.h_base.shape[0] * self.h_base.shape[1]
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grid_dim = cdiv(nitems, 256)
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memcpy_gpu[grid_dim, 256](self.h, self.h_base, nitems)
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def compare_hashes_level(self, lv):
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self.retval_int[0] = 0
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grid_dim = self._grid_dim(self.sims, self.line_use_counts[lv])
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diff_hash_gpu[grid_dim, self._block_dim](self.h, self.h_base, self.line_use, self.line_use_offsets[lv],
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self.line_use_counts[lv], self.retval_int)
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return self.retval_int[0]
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def calc_error_counts(self, sims=None):
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sims = min(sims or self.sims, self.sims)
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grid_dim = cdiv(self.s_len, 256)
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calc_error_counts_gpu[grid_dim, 256](self.s, sims, self.error_counts)
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return np.array(self.error_counts)
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@cuda.jit()
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def memcpy_gpu (src, dst, nitems):
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tid = cuda.grid(1)
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stride = cuda.gridDim.x * cuda.blockDim.x
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for i in range(tid, nitems, stride):
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dst.flat[i] = src.flat[i]
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@cuda.jit()
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def diff_hash_gpu(hbuf1, hbuf2, h_locs, h_locs_offset, h_locs_cnt, differs):
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x, y = cuda.grid(2)
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if x >= hbuf1.shape[1]: return
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if y >= h_locs_cnt: return
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h_loc = h_locs[h_locs_offset+y]
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if hbuf1[h_loc, x] != hbuf2[h_loc, x]:
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differs[0] = 1
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@cuda.jit()
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def calc_error_counts_gpu(s, sims, error_counts):
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x = cuda.grid(1)
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if x >= s.shape[1]: return
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cnt = 0
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for i in range(sims):
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cnt += (s[6,x,i] != s[8,x,i])
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error_counts[x] = cnt
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@cuda.jit()
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def wave_assign_gpu(c, s, c_locs, ppi_offset):
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@@ -425,7 +520,7 @@ _wave_eval_gpu = cuda.jit(_wave_eval, device=True)
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@cuda.jit()
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def wave_eval_gpu(ops, op_start, op_stop, cbuf, c_locs, c_caps, abuf, sim_start, sim_stop, delays, simctl_int, seed):
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def wave_eval_gpu(ops, op_start, op_stop, cbuf, c_locs, c_caps, hbuf, abuf, sim_start, sim_stop, delays, simctl_int, seed):
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x, y = cuda.grid(2)
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sim = sim_start + x
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op_idx = op_start + y
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@@ -437,7 +532,7 @@ def wave_eval_gpu(ops, op_start, op_stop, cbuf, c_locs, c_caps, abuf, sim_start,
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a_wr = op[7]
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a_wf = op[8]
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nrise, nfall = _wave_eval_gpu(op, cbuf, c_locs, c_caps, sim, delays, simctl_int[:, sim], seed)
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nrise, nfall = _wave_eval_gpu(op, cbuf, c_locs, c_caps, hbuf, sim, delays, simctl_int[:, sim], seed)
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# accumulate WSA into abuf
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if a_loc >= 0:
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@@ -8,9 +8,10 @@ from kyupy.logic import mvarray
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def test_xnor2_delays():
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op = (sim.XNOR2, 2, 0, 1, 3, 3, -1, 0, 0)
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#op = (0b0111, 4, 0, 1)
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c = np.full((4*16, 1), TMAX) # 4 waveforms of capacity 16
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c = np.full((4*16, 1), TMAX, dtype=np.float32) # 4 waveforms of capacity 16
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c_locs = np.zeros((4,), dtype='int')
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c_caps = np.zeros((4,), dtype='int')
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h = np.zeros((4, 1), dtype=np.float32)
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for i in range(4): c_locs[i], c_caps[i] = i*16, 16 # 1:1 mapping
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delays = np.zeros((1, 4, 2, 2))
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@@ -27,7 +28,7 @@ def test_xnor2_delays():
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def wave_assert(inputs, output):
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for i, a in zip(inputs, c.reshape(-1,16)): a[:len(i)] = i
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wave_eval_cpu(op, c, c_locs, c_caps, 0, delays, simctl_int)
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wave_eval_cpu(op, c, c_locs, c_caps, h, 0, delays, simctl_int, 0)
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for i, v in enumerate(output): np.testing.assert_allclose(c.reshape(-1,16)[2,i], v)
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wave_assert([[TMIN,TMAX],[TMIN,TMAX]], [TMIN,TMAX]) # XNOR(1,1) => 1
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@@ -40,9 +41,10 @@ def test_xnor2_delays():
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def test_nand_delays():
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op = (sim.NAND4, 4, 0, 1, 2, 3, -1, 0, 0)
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#op = (0b0111, 4, 0, 1)
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c = np.full((5*16, 1), TMAX) # 5 waveforms of capacity 16
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c = np.full((5*16, 1), TMAX, dtype=np.float32) # 5 waveforms of capacity 16
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c_locs = np.zeros((5,), dtype='int')
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c_caps = np.zeros((5,), dtype='int')
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h = np.zeros((5, 1), dtype=np.float32)
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for i in range(5): c_locs[i], c_caps[i] = i*16, 16 # 1:1 mapping
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@@ -64,7 +66,7 @@ def test_nand_delays():
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def wave_assert(inputs, output):
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for i, a in zip(inputs, c.reshape(-1,16)): a[:len(i)] = i
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wave_eval_cpu(op, c, c_locs, c_caps, 0, delays, simctl_int)
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wave_eval_cpu(op, c, c_locs, c_caps, h, 0, delays, simctl_int, 0)
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for i, v in enumerate(output): np.testing.assert_allclose(c.reshape(-1,16)[4,i], v)
|
||||
|
||||
wave_assert([[TMAX,TMAX],[TMAX,TMAX],[TMIN,TMAX],[TMIN,TMAX]], [TMIN,TMAX]) # NAND(0,0,1,1) => 1
|
||||
|
||||
Reference in new issue
Block a user