beginning simple always block parsing in verilog

src/kyupy/verilog.py

@@ -61,6 +61,10 @@ class VerilogTransformer(Transformer):
                 pinmap[idx] = p
         return Instantiation(args[0], args[1], pinmap)
 
+    @staticmethod
+    def simple_dff(args):
+        return Instantiation('DFF', args[1], {'d': args[2], 'clk': args[0], 'q': args[1]} )
+
     def range(self, args):
         left = int(args[0].value)
         right = int(args[1].value) if len(args) > 1 else left
@@ -110,6 +114,7 @@ class VerilogTransformer(Transformer):
     def output(self, args): return self.declaration("output", args)
     def inout(self, args): return self.declaration("input", args)  # just treat as input
     def wire(self, args): return self.declaration("wire", args)
+    def reg(self, args): pass #return self.declaration("wire", args)  # treat as wire
 
     def module(self, args):
         c = Circuit(args[0])
@@ -235,14 +240,16 @@ GRAMMAR = r"""
     start: (module)*
     module: "module" name parameters ";" (_statement)* "endmodule"
     parameters: "(" [ _namelist ] ")"
-    _statement: input | output | inout | tri | wire | assign | instantiation
+    _statement: input | output | inout | tri | wire | reg | assign | instantiation | simple_dff
     input: "input" range? _namelist ";"
     output: "output" range? _namelist ";"
     inout: "inout" range? _namelist ";"
     tri: "tri" range? _namelist ";"
     wire: "wire" range? _namelist ";"
+    reg: "reg" range? _namelist ";"
     assign: "assign" sigsel "=" sigsel ";"
     instantiation: name name "(" [ pin ( "," pin )* ] ")" ";"
+    simple_dff: "always" "@" "(" "posedge" name ")" sigsel "<=" sigsel ";"
     pin: namedpin | sigsel
     namedpin: "." name "(" sigsel? ")"
     range: "[" /[0-9]+/ (":" /[0-9]+/)? "]"

tests/map_to_minimal.abc

@@ -1,3 +1,5 @@
+# abc -f map_to_minimal.abc
+
 read kyupy_simprims.genlib
 read -m all_kyupy_simprims.v
 fraig