Documentation, cleanup, multi-valued logic
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@@ -20,15 +20,10 @@ Circuit Graph - :mod:`kyupy.circuit`
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.. autoclass:: kyupy.circuit.Circuit
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:members:
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M-Valued Logic - :mod:`kyupy.logic`
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-----------------------------------
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Multi-Valued Logic - :mod:`kyupy.logic`
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---------------------------------------
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.. automodule:: kyupy.logic
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:members:
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.. autoclass:: kyupy.logic.MVArray
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:members:
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.. autoclass:: kyupy.logic.BPArray
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:members:
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+36
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@@ -1,12 +1,42 @@
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Parsers
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=======
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bench
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KyuPy contains simple (and often incomplete) parsers for common file formats.
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These parsers are tailored to the most common use-cases to keep the grammars and the code-base as simple as possible.
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verilog
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SDF
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STIL
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Each of the modules export a function ``parse()`` for parsing a string directly and a function
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``load()`` for loading a file. Files with a '.gz' extension are uncompressed on-the-fly.
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Verilog - :mod:`kyupy.verilog`
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------------------------------
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.. automodule:: kyupy.verilog
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:members: parse, load
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Bench Format - :mod:`kyupy.bench`
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---------------------------------
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.. automodule:: kyupy.bench
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:members: parse, load
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Standard Test Interface Language - :mod:`kyupy.stil`
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----------------------------------------------------
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.. automodule:: kyupy.stil
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:members: parse, load
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.. autoclass:: kyupy.stil.StilFile
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:members:
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Standard Delay Format - :mod:`kyupy.sdf`
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----------------------------------------
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.. automodule:: kyupy.sdf
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:members: parse, load
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.. autoclass:: kyupy.sdf.DelayFile
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:members:
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+14
-2
@@ -1,8 +1,20 @@
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Simulators
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==========
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Logic Sim
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Logic Simulation - :mod:`kyupy.logic_sim`
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-----------------------------------------
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Wave Sim
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.. autoclass:: kyupy.logic_sim.LogicSim
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:members:
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Timing Simulation - :mod:`kyupy.wave_sim`
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-----------------------------------------
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.. automodule:: kyupy.wave_sim
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.. autoclass:: kyupy.wave_sim.WaveSim
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:members:
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.. autoclass:: kyupy.wave_sim.WaveSimCuda
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:members:
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