better docs and repr
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@@ -492,7 +492,7 @@ class LogicSim4V(sim.SimOps):
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self._full_mask = np.full(self.c.shape[-1], 255, dtype=np.uint8)
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self._full_mask = np.full(self.c.shape[-1], 255, dtype=np.uint8)
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def __repr__(self):
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def __repr__(self):
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return f'{{name: "{self.circuit.name}", sims: {self.sims}, c_bytes: {eng(self.c.nbytes)}}}'
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return f'{{name: "{self.circuit.name}", sims: {self.sims}, s_len: {self.s_len}, c_bytes: {eng(self.c.nbytes)}}}'
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def s_to_c(self):
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def s_to_c(self):
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"""Assigns the values from ``self.s_assign`` to the inputs of the combinational portion.
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"""Assigns the values from ``self.s_assign`` to the inputs of the combinational portion.
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@@ -330,11 +330,16 @@ class SimOps:
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self.prim_counts = dict(d)
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self.prim_counts = dict(d)
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self.pi_s_locs = np.flatnonzero(self.c_locs[self.ppi_offset+np.arange(len(self.circuit.io_nodes))] >= 0)
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self.pi_s_locs = np.flatnonzero(self.c_locs[self.ppi_offset+np.arange(len(self.circuit.io_nodes))] >= 0)
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"""Locations in pattern array (axis 0) of all primary inputs (excluding flip-flops)."""
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self.po_s_locs = np.flatnonzero(self.c_locs[self.ppo_offset+np.arange(len(self.circuit.io_nodes))] >= 0)
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self.po_s_locs = np.flatnonzero(self.c_locs[self.ppo_offset+np.arange(len(self.circuit.io_nodes))] >= 0)
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"""Locations in pattern array (axis 0) of all primary outputs (excluding flip-flops)."""
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self.ppio_s_locs = np.arange(len(self.circuit.io_nodes), self.s_len)
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self.ppio_s_locs = np.arange(len(self.circuit.io_nodes), self.s_len)
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"""Locations in pattern array (axis 0) of all flip-flops. Pseudo-primary inputs (PPI) and pseudo-primary outputs (PPO) share the same location."""
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self.pippi_s_locs = np.concatenate([self.pi_s_locs, self.ppio_s_locs])
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self.pippi_s_locs = np.concatenate([self.pi_s_locs, self.ppio_s_locs])
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"""Locations in pattern array (axis 0) of all primary and pseudo-primary inputs (input ports and flip-flops)."""
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self.poppo_s_locs = np.concatenate([self.po_s_locs, self.ppio_s_locs])
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self.poppo_s_locs = np.concatenate([self.po_s_locs, self.ppio_s_locs])
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"""Locations in pattern array (axis 0) of all primary and pseudo-primary outputs (output ports and flip-flops)."""
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self.pi_c_locs = self.c_locs[self.ppi_offset+self.pi_s_locs]
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self.pi_c_locs = self.c_locs[self.ppi_offset+self.pi_s_locs]
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self.po_c_locs = self.c_locs[self.ppo_offset+self.po_s_locs]
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self.po_c_locs = self.c_locs[self.ppo_offset+self.po_s_locs]
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