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one cell inherits name in substitute, sim fix

devel
Stefan Holst 1 year ago
parent
commit
50a5d8a290
  1. 10
      src/kyupy/circuit.py
  2. 4
      src/kyupy/sim.py

10
src/kyupy/circuit.py

@ -343,8 +343,15 @@ class Circuit: @@ -343,8 +343,15 @@ class Circuit:
the signal lines are connected appropriately. The number and arrangement
of the input and output ports must match the pins of the replaced node.
"""
ios = set(impl.io_nodes)
impl_in_lines = [n.outs[0] for n in impl.io_nodes if len(n.ins) == 0]
impl_out_lines = [n.ins[0] for n in impl.io_nodes if len(n.ins) > 0]
designated_cell = None
if len(impl_out_lines) > 0:
n = impl_out_lines[0].driver
while n.kind == '__fork__' and n not in ios:
n = n.ins[0].driver
designated_cell = n
node_in_lines = list(node.ins) + [None] * (len(impl_in_lines)-len(node.ins))
node_out_lines = list(node.outs) + [None] * (len(impl_out_lines)-len(node.outs))
assert len(node_in_lines) == len(impl_in_lines)
@ -356,7 +363,8 @@ class Circuit: @@ -356,7 +363,8 @@ class Circuit:
ios = set(impl.io_nodes)
for n in impl.nodes: # add all nodes to main circuit
if n not in ios:
node_map[n] = Node(self, node.name + '~' + n.name, n.kind)
suffix = '' if n == designated_cell else f'~{n.name}'
node_map[n] = Node(self, node.name + suffix, n.kind)
elif len(n.outs) > 0 and len(n.ins) > 0: # output is also read by impl. circuit, need to add a fork.
node_map[n] = Node(self, node.name + '~' + n.name)
for l in impl.lines: # add all internal lines to main circuit

4
src/kyupy/sim.py

@ -161,10 +161,10 @@ class SimOps: @@ -161,10 +161,10 @@ class SimOps:
self.s_len = len(circuit.s_nodes)
if isinstance(c_caps, int):
c_caps = [c_caps] * len(circuit.lines)
c_caps = [c_caps] * (len(circuit.lines)+3)
if a_ctrl is None:
a_ctrl = np.zeros((len(circuit.lines), 3), dtype=np.int32)
a_ctrl = np.zeros((len(circuit.lines)+3, 3), dtype=np.int32) # add 3 for zero, tmp, tmp2
a_ctrl[:,0] = -1
# special locations and offsets in c_locs/c_caps

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