From 3b7106be80c14ec6bd40eeaff338454d6309f8f6 Mon Sep 17 00:00:00 2001 From: Stefan Holst Date: Thu, 7 Nov 2024 17:06:00 +0900 Subject: [PATCH] fix deferred assignments --- src/kyupy/verilog.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/kyupy/verilog.py b/src/kyupy/verilog.py index 0938a81..1a8eeb8 100644 --- a/src/kyupy/verilog.py +++ b/src/kyupy/verilog.py @@ -144,6 +144,7 @@ class VerilogTransformer(Transformer): c.io_nodes[positions[name]] = n if sd.kind == 'input': Line(c, n, Node(c, name)) + deferred_assignments = set() while len(assignments) > 0: more_assignments = [] for target, source in assignments: # pass 1.5: process signal assignments @@ -163,7 +164,7 @@ class VerilogTransformer(Transformer): source_sigs.append(s) for t, s in zip(target_sigs, source_sigs): if t in c.forks: - assert s not in c.forks, 'assignment between two driven signals' + assert s not in c.forks, f'assignment between two driven signals: source={s} target={t}' Line(c, c.forks[t], Node(c, s)) elif s in c.forks: assert t not in c.forks, 'assignment between two driven signals' @@ -173,7 +174,11 @@ class VerilogTransformer(Transformer): const_count += 1 Line(c, cnode, Node(c, t)) else: - more_assignments.append((target, source)) + if (t, s) in deferred_assignments: + log.info(f'ignoring: assign {t} = {s}') + else: + more_assignments.append((t, s)) + deferred_assignments.add((t, s)) assignments = more_assignments for stmt in args[2:]: # pass 2: connect signals to readers if isinstance(stmt, Instantiation):