From 187d176cfd7395be2781731937cd4b50e81ad6c8 Mon Sep 17 00:00:00 2001
From: Stefan Holst <holst@csn.kyutech.ac.jp>
Date: Mon, 2 Jun 2025 12:20:42 +0900
Subject: [PATCH] partial ternary if support

---
 src/kyupy/__init__.py |  2 +-
 src/kyupy/verilog.py  | 21 +++++++++++++++++----
 2 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/src/kyupy/__init__.py b/src/kyupy/__init__.py
index a5d6a04..b473546 100644
--- a/src/kyupy/__init__.py
+++ b/src/kyupy/__init__.py
@@ -183,7 +183,7 @@ class Log:
             return
         t = time.perf_counter() - self.start
         self.logfile.write(f'# {t:011.3f} {level} {message}\n')
-        self.logfile.flush()
+        #self.logfile.flush()
         self._limit -= 1
 
     def info(self, message):
diff --git a/src/kyupy/verilog.py b/src/kyupy/verilog.py
index 1a8eeb8..bcb982f 100644
--- a/src/kyupy/verilog.py
+++ b/src/kyupy/verilog.py
@@ -73,7 +73,7 @@ class VerilogTransformer(Transformer):
         elif "'" in args[0]:
             width, rest = args[0].split("'")
             width = int(width)
-            base, const = rest[0], rest[1:]
+            base, const = rest[0], rest[1:].replace('x','0')
             const = int(const, {'b': 2, 'd':10, 'h':16}[base.lower()])
             l = []
             for _ in range(width):
@@ -92,6 +92,14 @@ class VerilogTransformer(Transformer):
                 sigs.append(a)
         return sigs
 
+    def ternaryif(self, args):
+        sel = args[0]
+        ctrue = args[1]
+        cfalse = args[2]
+        print(f"got ternary if {args[0]} {args[1]}")
+        
+        return args[1]
+
     def declaration(self, kind, args):
         rnge = None
         if isinstance(args[0], range):
@@ -145,6 +153,7 @@ class VerilogTransformer(Transformer):
                     if sd.kind == 'input':
                         Line(c, n, Node(c, name))
         deferred_assignments = set()
+        ignored = 0
         while len(assignments) > 0:
             more_assignments = []
             for target, source in assignments:  # pass 1.5: process signal assignments
@@ -175,11 +184,14 @@ class VerilogTransformer(Transformer):
                         Line(c, cnode, Node(c, t))
                     else:
                         if (t, s) in deferred_assignments:
-                            log.info(f'ignoring: assign {t} = {s}')
+                            #log.info(f'ignoring: assign {t} = {s}')
+                            ignored += 1
                         else:
                             more_assignments.append((t, s))
                             deferred_assignments.add((t, s)) 
             assignments = more_assignments
+        if ignored > 0:
+            log.warn(f'ignored {ignored} assignments')
         for stmt in args[2:]:  # pass 2: connect signals to readers
             if isinstance(stmt, Instantiation):
                 for p, s in stmt.pins.items():
@@ -235,10 +247,11 @@ GRAMMAR = r"""
     pin: namedpin | sigsel
     namedpin: "." name "(" sigsel? ")"
     range: "[" /[0-9]+/ (":" /[0-9]+/)? "]"
-    sigsel: name range? | concat
+    sigsel: name range? | concat | ternaryif
     concat: "{" sigsel ( "," sigsel )*  "}"
+    ternaryif: sigsel "?" sigsel ":" sigsel
     _namelist: name ( "," name )*
-    name: ( /[a-z_][a-z0-9_]*/i | /\\[^\t \r\n]+[\t \r\n]/i | /[0-9]+'[bdh][0-9a-f]+/i )
+    name: ( /[a-z_][a-z0-9_]*/i | /\\[^\t \r\n]+[\t \r\n]/i | /[0-9]+'[bdh][x0-9a-f]+/i )
     %import common.NEWLINE
     COMMENT: /\/\*(\*(?!\/)|[^*])*\*\// | /\(\*(\*(?!\))|[^*])*\*\)/ |  "//" /(.)*/ NEWLINE
     %ignore ( /\r?\n/ | COMMENT )+