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# edf2bench v0.8
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# (!) 1997-2003 Giovanni Squillero <giovanni.squillero@polito.it>
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#
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# Edf source: "b01/b01.edf"
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# 2 inputs
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# 2 outputs
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# 5 D-type flipflops
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# 10 inverters
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# 39 gates (1 and, 28 nand, 1 or, 10 not)
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INPUT(LINE1)
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INPUT(LINE2)
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OUTPUT(OUTP_REG)
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OUTPUT(OVERFLW_REG)
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OVERFLW_REG = DFF(U34)
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STATO_REG_2_ = DFF(U45)
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STATO_REG_1_ = DFF(U36)
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STATO_REG_0_ = DFF(U35)
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OUTP_REG = DFF(U44)
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U34 = AND(STATO_REG_1_, U38, STATO_REG_0_)
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U35 = NAND(U68, U67, U66, U65)
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U36 = NAND(U57, U55, U56)
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U37 = OR(LINE2, LINE1)
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U38 = NOT(STATO_REG_2_)
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U39 = NOT(STATO_REG_1_)
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U40 = NOT(LINE2)
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U41 = NOT(LINE1)
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U42 = NOT(STATO_REG_0_)
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U43 = NAND(STATO_REG_1_, U42)
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U44 = NAND(U73, U72)
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U45 = NAND(U60, U59)
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U46 = NAND(U70, U69)
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U47 = NAND(LINE1, LINE2)
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U48 = NAND(STATO_REG_2_, U43)
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U49 = NOT(U37)
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U50 = NAND(U49, U42)
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U51 = NOT(U47)
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U52 = NOT(U43)
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U53 = NAND(U47, U43)
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U54 = NAND(STATO_REG_2_, U47)
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U55 = NAND(STATO_REG_0_, U39, U47)
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U56 = NAND(U52, U54)
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U57 = NAND(U62, U61, STATO_REG_2_)
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U58 = NOT(U48)
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U59 = NAND(U53, U38)
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U60 = NAND(U50, U39, STATO_REG_2_)
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U61 = NAND(STATO_REG_1_, U49)
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U62 = NAND(U37, U42)
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U63 = NAND(STATO_REG_0_, U47)
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U64 = NAND(U51, U42)
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U65 = NAND(U64, U63, U39, U38)
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U66 = NAND(U43, U37, STATO_REG_2_)
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U67 = NAND(U34, U47)
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U68 = NAND(U51, U52)
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U69 = NAND(LINE1, U40)
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U70 = NAND(LINE2, U41)
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U71 = NOT(U46)
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U72 = NAND(U58, U71)
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U73 = NAND(U46, U48)
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+96
@@ -0,0 +1,96 @@
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//
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// Milkyway Hierarchical Verilog Dump:
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// Generated on 04/25/2017 at 20:29:24
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// Design Generated by Consolidated Verilog Reader
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// File produced by Consolidated Verilog Writer
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// Library Name :lib_mw
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// Cell Name :b01
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// Hierarchy delimiter:'/'
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// Write Command : write_verilog b01.v -no_physical_only_cells -no_corner_pad_cells
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// -no_pad_filler_cells
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//
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module b01 (line1 , Scan_Out , overflw , outp , Scan_In , Scan_Enable ,
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clock , reset , line2 );
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input line1 ;
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output Scan_Out ;
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output overflw ;
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output outp ;
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input Scan_In ;
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input Scan_Enable ;
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input clock ;
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input reset ;
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input line2 ;
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assign Scan_Out = overflw ;
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SDFFARX1 stato_reg_1_0 (.QN ( n137 ) , .Q ( stato_1_N ) , .CLK ( clock )
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, .RSTB ( n86 ) , .SE ( Scan_Enable ) , .SI ( stato_0_N ) , .D ( n53 ) ) ;
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INVX0 U1 (.ZN ( n1 ) , .INP ( n105 ) ) ;
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SDFFARX1 outp_reg (.Q ( outp ) , .CLK ( clock ) , .RSTB ( n86 )
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, .SE ( Scan_Enable ) , .SI ( Scan_In ) , .D ( n54 ) ) ;
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SDFFARX1 stato_reg_2_0 (.QN ( n148 ) , .Q ( stato_2_N ) , .CLK ( clock )
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, .RSTB ( n86 ) , .SE ( Scan_Enable ) , .SI ( stato_1_N ) , .D ( n55 ) ) ;
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SDFFARX1 stato_reg_0_0 (.QN ( n149 ) , .Q ( stato_0_N ) , .CLK ( clock )
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, .RSTB ( n86 ) , .SE ( Scan_Enable ) , .SI ( outp ) , .D ( n56 ) ) ;
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SDFFARX1 overflw_reg (.Q ( overflw ) , .CLK ( clock ) , .RSTB ( n86 )
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, .SE ( Scan_Enable ) , .SI ( stato_2_N ) , .D ( n61 ) ) ;
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AND2X1 U108 (.IN1 ( n1 ) , .IN2 ( stato_0_N ) , .Q ( n133 ) ) ;
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AND2X1 U109 (.IN1 ( n142 ) , .IN2 ( n136 ) , .Q ( n100 ) ) ;
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NAND2X0 U110 (.IN1 ( n129 ) , .IN2 ( n128 ) , .QN ( n131 ) ) ;
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NAND2X0 U111 (.IN1 ( n144 ) , .IN2 ( n132 ) , .QN ( n92 ) ) ;
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NOR2X0 U112 (.QN ( n132 ) , .IN1 ( n133 ) , .IN2 ( n147 ) ) ;
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OR2X1 U113 (.IN2 ( n1 ) , .IN1 ( n96 ) , .Q ( n144 ) ) ;
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NAND2X0 U114 (.IN1 ( line1 ) , .IN2 ( n134 ) , .QN ( n128 ) ) ;
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INVX0 U115 (.ZN ( n134 ) , .INP ( line2 ) ) ;
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AND2X1 U116 (.IN1 ( n135 ) , .IN2 ( n148 ) , .Q ( n61 ) ) ;
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NOR2X0 U117 (.QN ( n135 ) , .IN1 ( n149 ) , .IN2 ( n137 ) ) ;
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NOR2X0 U118 (.QN ( n136 ) , .IN1 ( n137 ) , .IN2 ( n149 ) ) ;
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NAND2X0 U119 (.IN1 ( n92 ) , .IN2 ( n137 ) , .QN ( n91 ) ) ;
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AND2X1 U120 (.IN1 ( stato_2_N ) , .IN2 ( n131 ) , .Q ( n147 ) ) ;
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NAND2X1 U121 (.IN2 ( n148 ) , .IN1 ( n109 ) , .QN ( n108 ) ) ;
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NOR2X0 U122 (.QN ( n130 ) , .IN1 ( n1 ) , .IN2 ( n148 ) ) ;
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NOR2X0 U123 (.QN ( n97 ) , .IN1 ( n104 ) , .IN2 ( n105 ) ) ;
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AND2X1 U124 (.IN1 ( n106 ) , .IN2 ( n148 ) , .Q ( n104 ) ) ;
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INVX0 U125 (.ZN ( n86 ) , .INP ( reset ) ) ;
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NAND2X1 U127 (.IN2 ( n115 ) , .IN1 ( n114 ) , .QN ( n54 ) ) ;
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NAND2X0 U128 (.IN1 ( stato_1_N ) , .IN2 ( n149 ) , .QN ( n140 ) ) ;
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NAND2X0 U130 (.IN1 ( n129 ) , .IN2 ( n128 ) , .QN ( n142 ) ) ;
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NAND2X0 U131 (.IN1 ( n129 ) , .IN2 ( n128 ) , .QN ( n103 ) ) ;
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NAND2X0 U134 (.IN1 ( line2 ) , .IN2 ( line1 ) , .QN ( n105 ) ) ;
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NAND2X0 U135 (.IN1 ( line2 ) , .IN2 ( n84 ) , .QN ( n129 ) ) ;
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INVX0 U136 (.ZN ( n84 ) , .INP ( line1 ) ) ;
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NAND2X0 U137 (.IN1 ( stato_1_N ) , .IN2 ( n149 ) , .QN ( n106 ) ) ;
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NAND2X0 U138 (.IN1 ( n149 ) , .IN2 ( n148 ) , .QN ( n96 ) ) ;
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NOR2X0 U139 (.QN ( n125 ) , .IN1 ( stato_1_N ) , .IN2 ( n1 ) ) ;
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NAND2X0 U140 (.IN1 ( n105 ) , .IN2 ( n140 ) , .QN ( n109 ) ) ;
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NOR2X0 U141 (.QN ( n122 ) , .IN1 ( n130 ) , .IN2 ( n140 ) ) ;
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NOR2X0 U142 (.QN ( n114 ) , .IN1 ( n117 ) , .IN2 ( n118 ) ) ;
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NAND2X0 U143 (.IN1 ( n117 ) , .IN2 ( n105 ) , .QN ( n120 ) ) ;
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NAND2X0 U144 (.IN1 ( n107 ) , .IN2 ( n108 ) , .QN ( n55 ) ) ;
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NAND2X0 U145 (.IN1 ( n120 ) , .IN2 ( n119 ) , .QN ( n53 ) ) ;
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NAND2X0 U146 (.IN1 ( n91 ) , .IN2 ( n90 ) , .QN ( n56 ) ) ;
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NAND2X0 U147 (.IN1 ( n110 ) , .IN2 ( n137 ) , .QN ( n107 ) ) ;
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NOR2X0 U148 (.QN ( n119 ) , .IN1 ( n123 ) , .IN2 ( n122 ) ) ;
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NOR2X0 U149 (.QN ( n90 ) , .IN1 ( n98 ) , .IN2 ( n97 ) ) ;
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INVX0 U150 (.ZN ( n145 ) , .INP ( n112 ) ) ;
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NAND2X0 U151 (.IN1 ( n105 ) , .IN2 ( n146 ) , .QN ( n110 ) ) ;
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NOR2X0 U152 (.QN ( n146 ) , .IN1 ( n147 ) , .IN2 ( n145 ) ) ;
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NOR2X0 U153 (.QN ( n123 ) , .IN1 ( n124 ) , .IN2 ( n149 ) ) ;
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NOR2X0 U154 (.QN ( n98 ) , .IN1 ( n99 ) , .IN2 ( n1 ) ) ;
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NOR2X0 U155 (.QN ( n124 ) , .IN1 ( n126 ) , .IN2 ( n125 ) ) ;
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NOR2X0 U156 (.QN ( n99 ) , .IN1 ( n100 ) , .IN2 ( n61 ) ) ;
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NAND2X0 U157 (.IN1 ( stato_2_N ) , .IN2 ( n140 ) , .QN ( n116 ) ) ;
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NAND2X0 U158 (.IN1 ( stato_2_N ) , .IN2 ( stato_0_N ) , .QN ( n112 ) ) ;
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NAND2X0 U159 (.IN1 ( n137 ) , .IN2 ( stato_2_N ) , .QN ( n121 ) ) ;
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NAND2X0 U160 (.IN1 ( stato_2_N ) , .IN2 ( n1 ) , .QN ( n127 ) ) ;
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NAND2X0 U161 (.IN1 ( n142 ) , .IN2 ( n116 ) , .QN ( n115 ) ) ;
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NOR2X0 U162 (.QN ( n118 ) , .IN1 ( n131 ) , .IN2 ( n112 ) ) ;
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NOR2X0 U163 (.QN ( n117 ) , .IN1 ( n121 ) , .IN2 ( n142 ) ) ;
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NAND2X0 U164 (.IN1 ( n127 ) , .IN2 ( n113 ) , .QN ( n126 ) ) ;
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NAND2X0 U165 (.IN1 ( stato_2_N ) , .IN2 ( n103 ) , .QN ( n113 ) ) ;
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endmodule
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import pytest
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@pytest.fixture
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def mydir():
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import os
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from pathlib import Path
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return Path(os.path.realpath(os.path.join(os.getcwd(), os.path.dirname(__file__))))
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@@ -0,0 +1,29 @@
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(DELAYFILE
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(SDFVERSION "OVI 2.1")
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(DESIGN "gates")
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(DIVIDER /)
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(VOLTAGE 1.20:1.20:1.20)
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(PROCESS "TYPICAL")
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(TEMPERATURE 25.00:25.00:25.00)
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(TIMESCALE 1ns)
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(CELL
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(CELLTYPE "NAND2X1")
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(INSTANCE nandgate)
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(DELAY
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(ABSOLUTE
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(IOPATH IN1 QN (0.099:0.103:0.103) (0.122:0.127:0.127))
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(IOPATH IN2 QN (0.083:0.086:0.086) (0.100:0.104:0.104))
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)
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)
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)
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(CELL
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(CELLTYPE "AND2X1")
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(INSTANCE andgate)
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(DELAY
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(ABSOLUTE
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(IOPATH IN1 Q (0.367:0.378:0.378) (0.351:0.377:0.377))
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(IOPATH IN2 Q (0.366:0.375:0.375) (0.359:0.370:0.370))
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)
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)
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)
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)
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@@ -0,0 +1,11 @@
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module gates (a, b, o0, o1 );
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input a;
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input b;
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output o0;
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output o1;
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AND2X1 andgate (.IN1 ( a ) , .IN2 ( b ) , .Q ( o0 ) ) ;
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NAND2X1 nandgate (.IN1 ( a ) , .IN2 ( b ) , .QN ( o1 ) ) ;
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endmodule
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from kyupy import bench
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def test_b01(mydir):
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with open(mydir / 'b01.bench', 'r') as f:
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c = bench.parse(f.read())
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assert 92 == len(c.nodes)
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c = bench.parse(mydir / 'b01.bench')
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assert 92 == len(c.nodes)
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def test_simple():
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c = bench.parse('input(a, b) output(z) z=and(a,b)')
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assert len(c.nodes) == 4
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assert len(c.interface) == 3
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from kyupy.circuit import Circuit, Node, Line
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def test_circuit():
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c = Circuit()
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in1 = Node(c, 'in1', 'buf')
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in2 = Node(c, 'in2', 'buf')
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out1 = Node(c, 'out1', 'buf')
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assert 'in1' in c.cells
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assert 'and1' not in c.cells
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c.interface[0] = in1
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c.interface[1] = in2
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c.interface[2] = out1
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and1 = Node(c, 'and1', kind='and')
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Line(c, in1, and1)
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Line(c, in2, and1)
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Line(c, and1, out1)
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assert len(in1.ins) == 0
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assert len(in1.outs) == 1
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assert len(in2.outs) == 1
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assert in1.outs[0].reader == and1
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assert in1.outs[0].driver == in1
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assert len(and1.ins) == 2
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assert len(and1.outs) == 1
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or1 = Node(c, 'or1', 'or')
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Line(c, and1, (or1, 1))
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or2 = Node(c, 'or2', 'or')
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or3 = Node(c, 'or3', 'or')
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assert or2.index == 5
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assert or3.index == 6
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assert len(c.nodes) == 7
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or2.remove()
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or3 = c.cells['or3']
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assert or3.index == 5
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assert 'or2' not in c.cells
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assert len(c.nodes) == 6
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c.cells['or3'].remove()
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assert 'or3' not in c.cells
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assert len(c.nodes) == 5
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repr(c)
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str(c)
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for n in c.topological_order():
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repr(n)
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@@ -0,0 +1,161 @@
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from kyupy.logic_sim import LogicSim
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from kyupy import bench
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from kyupy.packed_vectors import PackedVectors
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def test_vd1():
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c = bench.parse('input(x, y) output(a, o, n) a=and(x,y) o=or(x,y) n=not(x)')
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s = LogicSim(c, 4)
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assert len(s.interface) == 5
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p = PackedVectors(4, len(s.interface))
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p[0] = '00000'
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p[1] = '01000'
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p[2] = '10000'
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p[3] = '11000'
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s.assign(p)
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s.propagate()
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s.capture(p)
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assert p[0] == '00001'
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assert p[1] == '01011'
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assert p[2] == '10010'
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assert p[3] == '11110'
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def test_vd2():
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c = bench.parse('input(x, y) output(a, o, n) a=and(x,y) o=or(x,y) n=not(x)')
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s = LogicSim(c, 16, 2)
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assert len(s.interface) == 5
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p = PackedVectors(16, len(s.interface), 2)
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p[0] = '00000'
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p[1] = '01000'
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p[2] = '0-000'
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p[3] = '0X000'
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p[4] = '10000'
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p[5] = '11000'
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p[6] = '1-000'
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p[7] = '1X000'
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p[8] = '-0000'
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p[9] = '-1000'
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p[10] = '--000'
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p[11] = '-X000'
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p[12] = 'X0000'
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p[13] = 'X1000'
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p[14] = 'X-000'
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p[15] = 'XX000'
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s.assign(p)
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s.propagate()
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s.capture(p)
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assert p[0] == '00001'
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assert p[1] == '01011'
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assert p[2] == '0-0X1'
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assert p[3] == '0X0X1'
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assert p[4] == '10010'
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assert p[5] == '11110'
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assert p[6] == '1-X10'
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assert p[7] == '1XX10'
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assert p[8] == '-00XX'
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assert p[9] == '-1X1X'
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assert p[10] == '--XXX'
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assert p[11] == '-XXXX'
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assert p[12] == 'X00XX'
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assert p[13] == 'X1X1X'
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assert p[14] == 'X-XXX'
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assert p[15] == 'XXXXX'
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def test_vd3():
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c = bench.parse('input(x, y) output(a, o, n, xo) a=and(x,y) o=or(x,y) n=not(x) xo=xor(x,y)')
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s = LogicSim(c, 64, 3)
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assert len(s.interface) == 6
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p = PackedVectors(64, len(s.interface), 3)
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p[0] = '000010'
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p[1] = '010111'
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p[2] = '0-0X1X'
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p[3] = '0X0X1X'
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p[4] = '0R0R1R'
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p[5] = '0F0F1F'
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p[6] = '0P0P1P'
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p[7] = '0N0N1N'
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p[8] = '100101'
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p[9] = '111100'
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p[10] = '1-X10X'
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p[11] = '1XX10X'
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p[12] = '1RR10F'
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p[13] = '1FF10R'
|
||||
p[14] = '1PP10N'
|
||||
p[15] = '1NN10P'
|
||||
p[16] = '-00XXX'
|
||||
p[17] = '-1X1XX'
|
||||
p[18] = '--XXXX'
|
||||
p[19] = '-XXXXX'
|
||||
p[20] = '-RXXXX'
|
||||
p[21] = '-FXXXX'
|
||||
p[22] = '-PXXXX'
|
||||
p[23] = '-NXXXX'
|
||||
p[24] = 'X00XXX'
|
||||
p[25] = 'X1X1XX'
|
||||
p[26] = 'X-XXXX'
|
||||
p[27] = 'XXXXXX'
|
||||
p[28] = 'XRXXXX'
|
||||
p[29] = 'XFXXXX'
|
||||
p[30] = 'XPXXXX'
|
||||
p[31] = 'XNXXXX'
|
||||
p[32] = 'R00RFR'
|
||||
p[33] = 'R1R1FF'
|
||||
p[34] = 'R-XXFX'
|
||||
p[35] = 'RXXXFX'
|
||||
p[36] = 'RRRRFP'
|
||||
p[37] = 'RFPNFN'
|
||||
p[38] = 'RPPRFR'
|
||||
p[39] = 'RNRNFF'
|
||||
p[40] = 'F00FRF'
|
||||
p[41] = 'F1F1RR'
|
||||
p[42] = 'F-XXRX'
|
||||
p[43] = 'FXXXRX'
|
||||
p[44] = 'FRPNRN'
|
||||
p[45] = 'FFFFRP'
|
||||
p[46] = 'FPPFRF'
|
||||
p[47] = 'FNFNRR'
|
||||
p[48] = 'P00PNP'
|
||||
p[49] = 'P1P1NN'
|
||||
p[50] = 'P-XXNX'
|
||||
p[51] = 'PXXXNX'
|
||||
p[52] = 'PRPRNR'
|
||||
p[53] = 'PFPFNF'
|
||||
p[54] = 'PPPPNP'
|
||||
p[55] = 'PNPNNN'
|
||||
p[56] = 'N00NPN'
|
||||
p[57] = 'N1N1PP'
|
||||
p[58] = 'N-XXPX'
|
||||
p[59] = 'NXXXPX'
|
||||
p[60] = 'NRRNPF'
|
||||
p[61] = 'NFFNPR'
|
||||
p[62] = 'NPPNPN'
|
||||
p[63] = 'NNNNPP'
|
||||
expect = p.copy()
|
||||
s.assign(p)
|
||||
s.propagate()
|
||||
s.capture(p)
|
||||
for i in range(64):
|
||||
assert p[i] == expect[i]
|
||||
|
||||
|
||||
def test_b01(mydir):
|
||||
c = bench.parse(mydir / 'b01.bench')
|
||||
|
||||
# 2-valued
|
||||
s = LogicSim(c, 8)
|
||||
assert len(s.interface) == 9
|
||||
t = PackedVectors(8, len(s.interface))
|
||||
t.randomize()
|
||||
s.assign(t)
|
||||
s.propagate()
|
||||
s.capture(t)
|
||||
|
||||
# 8-valued
|
||||
s = LogicSim(c, 8, 3)
|
||||
t = PackedVectors(8, len(s.interface), 3)
|
||||
t.randomize()
|
||||
s.assign(t)
|
||||
s.propagate()
|
||||
s.capture(t)
|
||||
@@ -0,0 +1,88 @@
|
||||
from kyupy.packed_vectors import PackedVectors
|
||||
|
||||
|
||||
def test_basic():
|
||||
ba = PackedVectors(8, 1, 1)
|
||||
assert '0\n0\n0\n0\n0\n0\n0\n0' == str(ba)
|
||||
ba.set_value(0, 0, 1)
|
||||
ba.set_value(1, 0, 'H')
|
||||
ba.set_value(2, 0, 'h')
|
||||
ba.set_value(3, 0, True)
|
||||
ba.set_value(4, 0, 0)
|
||||
ba.set_value(5, 0, 'L')
|
||||
ba.set_value(6, 0, 'l')
|
||||
ba.set_value(7, 0, False)
|
||||
assert '1\n1\n1\n1\n0\n0\n0\n0' == str(ba)
|
||||
ba.set_value(1, 0, '0')
|
||||
ba.set_value(5, 0, '1')
|
||||
assert '1\n0\n1\n1\n0\n1\n0\n0' == str(ba)
|
||||
ba = PackedVectors(8, 1, 2)
|
||||
assert '-\n-\n-\n-\n-\n-\n-\n-' == str(ba)
|
||||
ba.set_value(0, 0, 1)
|
||||
ba.set_value(7, 0, 0)
|
||||
ba.set_value(4, 0, 'X')
|
||||
assert '1\n-\n-\n-\nX\n-\n-\n0' == str(ba)
|
||||
ba.set_value(4, 0, '-')
|
||||
assert '1\n-\n-\n-\n-\n-\n-\n0' == str(ba)
|
||||
ba = PackedVectors(8, 2, 2)
|
||||
assert '--\n--\n--\n--\n--\n--\n--\n--' == str(ba)
|
||||
ba.set_value(0, 0, '1')
|
||||
ba.set_value(7, 1, '0')
|
||||
ba.set_values(1, 'XX')
|
||||
assert '1-\nXX\n--\n--\n--\n--\n--\n-0' == str(ba)
|
||||
|
||||
|
||||
def test_8v():
|
||||
ba = PackedVectors(1, 8, 3)
|
||||
assert '--------' == str(ba)
|
||||
ba.set_values(0, r'-x01^v\/')
|
||||
assert r'-X01PNFR' == str(ba)
|
||||
ba.set_values(0, '-XLHPNFR')
|
||||
assert r'-X01PNFR' == str(ba)
|
||||
ba.set_values(0, '-xlhpnfr')
|
||||
assert r'-X01PNFR' == str(ba)
|
||||
p1 = PackedVectors(1, 8, 1)
|
||||
p2 = PackedVectors(1, 8, 1)
|
||||
p1.set_values(0, '01010101')
|
||||
p2.set_values(0, '00110011')
|
||||
p = PackedVectors.from_pair(p1, p2)
|
||||
assert r'0FR10FR1' == str(p)
|
||||
p1 = PackedVectors(1, 8, 2)
|
||||
p2 = PackedVectors(1, 8, 2)
|
||||
p1.set_values(0, '0101-X-X')
|
||||
p2.set_values(0, '00110011')
|
||||
p = PackedVectors.from_pair(p1, p2)
|
||||
assert r'0FR1----' == str(p)
|
||||
p1.set_values(0, '0101-X-X')
|
||||
p2.set_values(0, '-X-X--XX')
|
||||
p = PackedVectors.from_pair(p1, p2)
|
||||
assert r'--------' == str(p)
|
||||
|
||||
|
||||
def test_slicing():
|
||||
lv = PackedVectors(3, 2, 1)
|
||||
assert '00\n00\n00' == str(lv)
|
||||
lv.set_value(1, 0, '1')
|
||||
lv.set_value(1, 1, '1')
|
||||
assert '00' == lv[0]
|
||||
assert '11' == lv[1]
|
||||
assert 3 == len(lv)
|
||||
lv2 = lv[1:3]
|
||||
assert 2 == len(lv2)
|
||||
assert '11' == lv2[0]
|
||||
assert '00' == lv2[1]
|
||||
|
||||
|
||||
def test_copy():
|
||||
lv1 = PackedVectors(8, 1, 1)
|
||||
lv1.set_values_for_position(0, '01010101')
|
||||
lv2 = PackedVectors(8, 1, 1)
|
||||
lv2.set_values_for_position(0, '00100101')
|
||||
diff = lv1.diff(lv2)
|
||||
lv3 = lv1.copy(selection_mask=diff)
|
||||
assert str(lv3) == '1\n0\n1'
|
||||
lv4 = lv1.copy(selection_mask=~diff)
|
||||
assert str(lv4) == '0\n0\n1\n0\n1'
|
||||
lv5 = lv3 + lv4
|
||||
assert str(lv5) == '1\n0\n1\n0\n0\n1\n0\n1'
|
||||
|
||||
@@ -0,0 +1,100 @@
|
||||
from kyupy import sdf, verilog
|
||||
from kyupy.saed import pin_index
|
||||
|
||||
|
||||
def test_parse():
|
||||
test = '''
|
||||
(DELAYFILE
|
||||
(SDFVERSION "OVI 2.1")
|
||||
(DESIGN "test")
|
||||
(DATE "Wed May 31 14:46:06 2017")
|
||||
(VENDOR "saed90nm_max")
|
||||
(PROGRAM "Synopsys Design Compiler cmos-annotated")
|
||||
(VERSION "I-2013.12-ICC-SP3")
|
||||
(DIVIDER /)
|
||||
(VOLTAGE 1.20:1.20:1.20)
|
||||
(PROCESS "TYPICAL")
|
||||
(TEMPERATURE 25.00:25.00:25.00)
|
||||
(TIMESCALE 1ns)
|
||||
(CELL
|
||||
(CELLTYPE "b14")
|
||||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT U621/ZN U19246/IN1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT U13292/QN U19246/IN2 (0.001:0.001:0.001))
|
||||
(INTERCONNECT U15050/QN U19247/IN1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT U13293/QN U19247/IN2 (0.000:0.000:0.000) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "INVX2")
|
||||
(INSTANCE U78)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH INP ZN (0.201:0.227:0.227) (0.250:0.271:0.271))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SDFFARX1")
|
||||
(INSTANCE reg3_reg_1_0)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH (posedge CLK) Q (0.707:0.710:0.710) (0.737:0.740:0.740))
|
||||
(IOPATH (negedge RSTB) Q () (0.909:0.948:0.948))
|
||||
(IOPATH (posedge CLK) QN (0.585:0.589:0.589) (0.545:0.550:0.550))
|
||||
(IOPATH (negedge RSTB) QN (1.546:1.593:1.593) ())
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(WIDTH (posedge CLK) (0.284:0.284:0.284))
|
||||
(WIDTH (negedge CLK) (0.642:0.642:0.642))
|
||||
(SETUP (posedge D) (posedge CLK) (0.544:0.553:0.553))
|
||||
(SETUP (negedge D) (posedge CLK) (0.620:0.643:0.643))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.321:-0.331:-0.331))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.196:-0.219:-0.219))
|
||||
(RECOVERY (posedge RSTB) (posedge CLK) (-1.390:-1.455:-1.455))
|
||||
(HOLD (posedge RSTB) (posedge CLK) (1.448:1.509:1.509))
|
||||
(SETUP (posedge SE) (posedge CLK) (0.662:0.670:0.670))
|
||||
(SETUP (negedge SE) (posedge CLK) (0.698:0.702:0.702))
|
||||
(HOLD (posedge SE) (posedge CLK) (-0.435:-0.444:-0.444))
|
||||
(HOLD (negedge SE) (posedge CLK) (-0.291:-0.295:-0.295))
|
||||
(SETUP (posedge SI) (posedge CLK) (0.544:0.544:0.544))
|
||||
(SETUP (negedge SI) (posedge CLK) (0.634:0.688:0.688))
|
||||
(HOLD (posedge SI) (posedge CLK) (-0.317:-0.318:-0.318))
|
||||
(HOLD (negedge SI) (posedge CLK) (-0.198:-0.247:-0.247))
|
||||
(WIDTH (negedge RSTB) (0.345:0.345:0.345))
|
||||
)))
|
||||
'''
|
||||
df = sdf.parse(test)
|
||||
assert df.name == 'test'
|
||||
# print(f'DelayFile(name={df.name}, interconnects={len(df.interconnects)}, iopaths={len(df.iopaths)})')
|
||||
|
||||
|
||||
def test_b14(mydir):
|
||||
df = sdf.parse(mydir / 'b14.sdf.gz')
|
||||
assert df.name == 'b14'
|
||||
|
||||
|
||||
def test_gates(mydir):
|
||||
c = verilog.parse(mydir / 'gates.v')
|
||||
df = sdf.parse(mydir / 'gates.sdf')
|
||||
lt = df.annotation(c, pin_index, dataset=1)
|
||||
nand_a = c.cells['nandgate'].ins[0]
|
||||
nand_b = c.cells['nandgate'].ins[1]
|
||||
and_a = c.cells['andgate'].ins[0]
|
||||
and_b = c.cells['andgate'].ins[1]
|
||||
|
||||
assert lt[nand_a.index, 0, 0] == 0.103
|
||||
assert lt[nand_a.index, 0, 1] == 0.127
|
||||
|
||||
assert lt[nand_b.index, 0, 0] == 0.086
|
||||
assert lt[nand_b.index, 0, 1] == 0.104
|
||||
|
||||
assert lt[and_a.index, 0, 0] == 0.378
|
||||
assert lt[and_a.index, 0, 1] == 0.377
|
||||
|
||||
assert lt[and_b.index, 0, 0] == 0.375
|
||||
assert lt[and_b.index, 0, 1] == 0.370
|
||||
@@ -0,0 +1,9 @@
|
||||
from kyupy import stil
|
||||
|
||||
|
||||
def test_b14(mydir):
|
||||
s = stil.parse(mydir / 'b14.stil.gz')
|
||||
assert 10 == len(s.signal_groups)
|
||||
assert 1 == len(s.scan_chains)
|
||||
assert 3259 == len(s.calls)
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
from kyupy import verilog
|
||||
|
||||
|
||||
def test_b01(mydir):
|
||||
with open(mydir / 'b01.v', 'r') as f:
|
||||
modules = verilog.parse(f.read())
|
||||
assert modules is not None
|
||||
assert verilog.parse(mydir / 'b01.v') is not None
|
||||
|
||||
@@ -0,0 +1,138 @@
|
||||
import numpy as np
|
||||
from kyupy.wave_sim import WaveSim, wave_eval, TMIN, TMAX
|
||||
from kyupy.logic_sim import LogicSim
|
||||
from kyupy import verilog
|
||||
from kyupy import sdf
|
||||
from kyupy.saed import pin_index
|
||||
from kyupy.packed_vectors import PackedVectors
|
||||
from kyupy.wave_sim_cuda import WaveSimCuda
|
||||
|
||||
|
||||
def test_wave_eval():
|
||||
# SDF specifies IOPATH delays with respect to output polarity
|
||||
# SDF pulse rejection value is determined by IOPATH causing last transition and polarity of last transition
|
||||
line_times = np.zeros((3, 2, 2))
|
||||
line_times[0, 0, 0] = 0.1 # A -> Z rise delay
|
||||
line_times[0, 0, 1] = 0.2 # A -> Z fall delay
|
||||
line_times[0, 1, 0] = 0.1 # A -> Z negative pulse limit (terminate in rising Z)
|
||||
line_times[0, 1, 1] = 0.2 # A -> Z positive pulse limit
|
||||
line_times[1, 0, 0] = 0.3 # as above for B -> Z
|
||||
line_times[1, 0, 1] = 0.4
|
||||
line_times[1, 1, 0] = 0.3
|
||||
line_times[1, 1, 1] = 0.4
|
||||
|
||||
state = np.zeros((3*16, 1)) + TMAX # 3 waveforms of capacity 16
|
||||
state[::16, 0] = 16 # first entry is capacity
|
||||
a = state[0:16, 0]
|
||||
b = state[16:32, 0]
|
||||
z = state[32:, 0]
|
||||
sat = np.zeros((3, 2), dtype='int')
|
||||
sat[0] = 0, 16
|
||||
sat[1] = 16, 16
|
||||
sat[2] = 32, 16
|
||||
|
||||
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
|
||||
assert TMIN == z[0]
|
||||
|
||||
a[0] = TMIN
|
||||
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
|
||||
assert TMIN == z[0]
|
||||
|
||||
b[0] = TMIN
|
||||
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
|
||||
assert TMAX == z[0]
|
||||
|
||||
a[0] = 1 # A _/^^^
|
||||
b[0] = 2 # B __/^^
|
||||
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
|
||||
assert TMIN == z[0] # ^^^\___ B -> Z fall delay
|
||||
assert 2.4 == z[1]
|
||||
assert TMAX == z[2]
|
||||
|
||||
a[0] = TMIN # A ^^^^^^
|
||||
b[0] = TMIN # B ^^^\__
|
||||
b[1] = 2
|
||||
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
|
||||
assert 2.3 == z[0] # ___/^^^ B -> Z rise delay
|
||||
assert TMAX == z[1]
|
||||
|
||||
# pos pulse of 0.35 at B -> 0.45 after delays
|
||||
a[0] = TMIN # A ^^^^^^^^
|
||||
b[0] = TMIN
|
||||
b[1] = 2 # B ^^\__/^^
|
||||
b[2] = 2.35
|
||||
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
|
||||
assert 2.3 == z[0] # __/^^\__
|
||||
assert 2.75 == z[1]
|
||||
assert TMAX == z[2]
|
||||
|
||||
# neg pulse of 0.45 at B -> 0.35 after delays
|
||||
a[0] = TMIN # A ^^^^^^^^
|
||||
b[0] = 2 # B __/^^\__
|
||||
b[1] = 2.45
|
||||
b[2] = TMAX
|
||||
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
|
||||
assert TMIN == z[0] # ^^\__/^^
|
||||
assert 2.4 == z[1]
|
||||
assert 2.75 == z[2]
|
||||
assert TMAX == z[3]
|
||||
|
||||
# neg pulse of 0.35 at B -> 0.25 after delays (filtered)
|
||||
a[0] = TMIN # A ^^^^^^^^
|
||||
b[0] = 2 # B __/^^\__
|
||||
b[1] = 2.35
|
||||
b[2] = TMAX
|
||||
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
|
||||
assert TMIN == z[0] # ^^^^^^
|
||||
assert TMAX == z[1]
|
||||
|
||||
# pos pulse of 0.25 at B -> 0.35 after delays (filtered)
|
||||
a[0] = TMIN # A ^^^^^^^^
|
||||
b[0] = TMIN
|
||||
b[1] = 2 # B ^^\__/^^
|
||||
b[2] = 2.25
|
||||
wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
|
||||
assert TMAX == z[0] # ______
|
||||
|
||||
|
||||
def compare_to_logic_sim(wsim):
|
||||
tests = PackedVectors(wsim.sims, len(wsim.interface), 3)
|
||||
tests.randomize()
|
||||
wsim.assign(tests)
|
||||
wsim.propagate(8)
|
||||
cap = np.zeros((len(wsim.interface), wsim.sims))
|
||||
wsim.capture(probabilities=cap)
|
||||
|
||||
resp = tests.copy()
|
||||
|
||||
for iidx, inode in enumerate(wsim.interface):
|
||||
if len(inode.ins) > 0:
|
||||
for vidx in range(wsim.sims):
|
||||
resp.set_value(vidx, iidx, 0 if cap[iidx, vidx] < 0.5 else 1)
|
||||
|
||||
lsim = LogicSim(wsim.circuit, len(tests), 3)
|
||||
lsim.assign(tests)
|
||||
lsim.propagate()
|
||||
exp = tests.copy()
|
||||
lsim.capture(exp)
|
||||
|
||||
for i in range(8):
|
||||
exp_str = exp[i].replace('R', '1').replace('F', '0').replace('P', '0').replace('N', '1')
|
||||
res_str = resp[i].replace('R', '1').replace('F', '0').replace('P', '0').replace('N', '1')
|
||||
assert res_str == exp_str
|
||||
|
||||
|
||||
def test_b14(mydir):
|
||||
c = verilog.parse(mydir / 'b14.v.gz', branchforks=True)
|
||||
df = sdf.parse(mydir / 'b14.sdf.gz')
|
||||
lt = df.annotation(c, pin_index)
|
||||
wsim = WaveSim(c, lt, 8)
|
||||
compare_to_logic_sim(wsim)
|
||||
|
||||
|
||||
def test_b14_cuda(mydir):
|
||||
c = verilog.parse(mydir / 'b14.v.gz', branchforks=True)
|
||||
df = sdf.parse(mydir / 'b14.sdf.gz')
|
||||
lt = df.annotation(c, pin_index)
|
||||
wsim = WaveSimCuda(c, lt, 8)
|
||||
compare_to_logic_sim(wsim)
|
||||
Reference in new issue
Block a user