new logic sim interface prototype, simprim lib and test
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@@ -10,7 +10,7 @@ import math
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import numpy as np
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import numpy as np
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from . import numba, logic, hr_bytes, sim, eng, cdiv
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from . import numba, logic, hr_bytes, sim, eng, cdiv, batchrange
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from .circuit import Circuit
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from .circuit import Circuit
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@@ -363,6 +363,90 @@ def _prop_cpu(ops, c_locs, c, fault_line, fault_mask, fault_model):
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c[o0] = c[o0] ^ fault_mask
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c[o0] = c[o0] ^ fault_mask
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class LogicSim2V(sim.SimOps):
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"""A bit-parallel naïve combinational simulator for 2-valued logic.
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:param circuit: The circuit to simulate.
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:param sims: The number of parallel logic simulations to perform.
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:param c_reuse: If True, intermediate signal values may get overwritten when not needed anymore to save memory.
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:param strip_forks: If True, forks are not included in the simulation model to save memory and simulation time.
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Caveat: faults on fanout branches will not be injected if forks are stripped.
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"""
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def __init__(self, circuit: Circuit, sims: int = 8, c_reuse: bool = False, strip_forks: bool = False):
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super().__init__(circuit, c_reuse=c_reuse, strip_forks=strip_forks)
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self.sims = sims
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nbytes = cdiv(sims, 8)
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self.c = np.zeros((self.c_len, 1, nbytes), dtype=np.uint8)
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"""Logic values within the combinational portion of the circuit.
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In bit-parallel (bp) storage format.
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Storage locations are indirectly addressed.
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Data for line `l` is in `self.c[self.c_locs[l]]`.
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"""
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self.s_assign = np.zeros((self.s_len, self.sims), dtype=np.uint8)
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"""Logic values assigned to the ports and flip-flops of the circuit.
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The simulator reads (P)PI values from here.
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Values assigned to PO positions are ignored.
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This field is a 2-dimensional array and expects values in the mv storage format.
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First index is the port position (defined by `self.circuit.s_nodes`), second index is the pattern index (0 ... `self.sims-1`).
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"""
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self.s_result = np.zeros((self.s_len, self.sims), dtype=np.uint8)
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"""Logic values at the ports and flip-flops of the circuit after simulation.
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The simulator writes (P)PO values here.
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Values assigned to PI positions are ignored.
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This field is a 2-dimensional array and expects values in the mv storage format.
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First index is the port position (defined by `self.circuit.s_nodes`), second index is the pattern index (0 ... `self.sims-1`).
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"""
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self._full_mask = np.full(self.c.shape[-1], 255, dtype=np.uint8)
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def __repr__(self):
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return f'{{name: "{self.circuit.name}", sims: {self.sims}, c_bytes: {eng(self.c.nbytes)}}}'
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def s_to_c(self):
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"""Assigns the values from ``self.s_assign`` to the inputs of the combinational portion.
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"""
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self.c[self.pippi_c_locs] = logic.mv_to_bp(self.s_assign[self.pippi_s_locs])[:,:1,:]
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def c_prop(self, fault_line=-1, fault_model=2, fault_mask=None):
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if fault_mask is None:
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fault_mask = self._full_mask # default: full mask
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else:
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if len(fault_mask) < self.c.shape[-1]: # pad mask with 0's if necessary
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fault_mask2 = np.full(self.c.shape[-1], 0, dtype=np.uint8)
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fault_mask2[:len(fault_mask)] = fault_mask
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fault_mask = fault_mask2
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_prop_cpu(self.ops, self.c_locs, self.c, int(fault_line), fault_mask, int(fault_model))
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def c_to_s(self):
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"""Captures the results of the combinational portion into ``self.s_result``.
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"""
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self.s_result[self.poppo_s_locs] = logic.bp_to_mv(self.c[self.poppo_c_locs])[:,:self.sims] * logic.ONE
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def c_ppo_to_ppi(self):
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"""Copies the result data for all PPOs (flip-flops) to PPIs for a next simulation cycle.
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"""
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self.c[self.ppi_c_locs] = self.c[self.ppo_c_locs].copy() # copy prevents undefined behavior if (P)PIs are connected directly to (P)POs
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def allocate(self):
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"""Allocates a new pattern array with appropriate dimensions ``(self.s_len, self.sims)`` for one-pass simulation.
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"""
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return np.full((self.s_len, self.sims), logic.ZERO, dtype=np.uint8)
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def simulate(self, patterns, cycles:int = 1, fault_line=-1, fault_model=2, fault_mask=None):
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assert cycles >= 1
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for bo, bs in batchrange(patterns.shape[-1], self.sims):
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self.s_assign[self.pippi_s_locs, :bs] = patterns[self.pippi_s_locs, bo:bo+bs]
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self.s_to_c()
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for cycle in range(cycles):
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self.c_prop(fault_line=fault_line, fault_model=fault_model, fault_mask=fault_mask)
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if cycle < (cycles-1): self.c_ppo_to_ppi()
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self.c_to_s()
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patterns[self.poppo_s_locs, bo:bo+bs] = self.s_result[self.poppo_s_locs, :bs]
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class LogicSim6V(sim.SimOps):
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class LogicSim6V(sim.SimOps):
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"""A bit-parallel naïve combinational simulator for 6-valued logic.
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"""A bit-parallel naïve combinational simulator for 6-valued logic.
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@@ -0,0 +1,91 @@
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// Benchmark "all_kyupy_primitives" written by ABC on Sat Nov 1 23:49:37 2025
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module all_kyupy_primitives (
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i0, i1, i2, i3,
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\o[0] , \o[1] , \o[2] , \o[3] , \o[4] , \o[5] , \o[6] , \o[7] , \o[8] ,
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\o[9] , \o[10] , \o[11] , \o[12] , \o[13] , \o[14] , \o[15] , \o[16] ,
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\o[17] , \o[18] , \o[19] , \o[20] , \o[21] , \o[22] , \o[23] , \o[24] ,
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\o[25] , \o[26] , \o[27] , \o[28] , \o[29] );
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input i0, i1, i2, i3;
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output \o[0] , \o[1] , \o[2] , \o[3] , \o[4] , \o[5] , \o[6] , \o[7] ,
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\o[8] , \o[9] , \o[10] , \o[11] , \o[12] , \o[13] , \o[14] , \o[15] ,
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\o[16] , \o[17] , \o[18] , \o[19] , \o[20] , \o[21] , \o[22] , \o[23] ,
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\o[24] , \o[25] , \o[26] , \o[27] , \o[28] , \o[29] ;
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wire new_n42, new_n45, new_n48, new_n51, new_n52, new_n53, new_n54,
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new_n55, new_n57, new_n58, new_n59, new_n60, new_n61, new_n62, new_n63,
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new_n64, new_n65, new_n66, new_n67, new_n69, new_n70, new_n71, new_n72,
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new_n73, new_n74, new_n75, new_n76, new_n77, new_n78, new_n79, new_n83,
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new_n84, new_n88, new_n89, new_n93, new_n96, new_n99, new_n100,
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new_n101;
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INV1 g00(.i0(i1), .o(\o[1] ));
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AND2 g01(.i0(i1), .i1(i0), .o(\o[2] ));
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AND2 g02(.i0(\o[2] ), .i1(i2), .o(\o[3] ));
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AND2 g03(.i0(\o[3] ), .i1(i3), .o(\o[4] ));
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INV1 g04(.i0(\o[2] ), .o(\o[5] ));
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INV1 g05(.i0(\o[3] ), .o(\o[6] ));
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INV1 g06(.i0(\o[4] ), .o(\o[7] ));
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INV1 g07(.i0(i0), .o(new_n42));
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AND2 g08(.i0(\o[1] ), .i1(new_n42), .o(\o[11] ));
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INV1 g09(.i0(\o[11] ), .o(\o[8] ));
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INV1 g10(.i0(i2), .o(new_n45));
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AND2 g11(.i0(\o[11] ), .i1(new_n45), .o(\o[12] ));
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INV1 g12(.i0(\o[12] ), .o(\o[9] ));
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INV1 g13(.i0(i3), .o(new_n48));
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AND2 g14(.i0(\o[12] ), .i1(new_n48), .o(\o[13] ));
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INV1 g15(.i0(\o[13] ), .o(\o[10] ));
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AND2 g16(.i0(\o[1] ), .i1(i0), .o(new_n51));
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INV1 g17(.i0(new_n51), .o(new_n52));
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AND2 g18(.i0(i1), .i1(new_n42), .o(new_n53));
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INV1 g19(.i0(new_n53), .o(new_n54));
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AND2 g20(.i0(new_n54), .i1(new_n52), .o(new_n55));
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INV1 g21(.i0(new_n55), .o(\o[14] ));
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AND2 g22(.i0(i2), .i1(i1), .o(new_n57));
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INV1 g23(.i0(new_n57), .o(new_n58));
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AND2 g24(.i0(new_n45), .i1(\o[1] ), .o(new_n59));
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INV1 g25(.i0(new_n59), .o(new_n60));
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AND2 g26(.i0(new_n60), .i1(new_n58), .o(new_n61));
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INV1 g27(.i0(new_n61), .o(new_n62));
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AND2 g28(.i0(new_n62), .i1(i0), .o(new_n63));
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INV1 g29(.i0(new_n63), .o(new_n64));
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AND2 g30(.i0(new_n61), .i1(new_n42), .o(new_n65));
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INV1 g31(.i0(new_n65), .o(new_n66));
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AND2 g32(.i0(new_n66), .i1(new_n64), .o(new_n67));
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INV1 g33(.i0(new_n67), .o(\o[15] ));
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AND2 g34(.i0(i3), .i1(new_n45), .o(new_n69));
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INV1 g35(.i0(new_n69), .o(new_n70));
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AND2 g36(.i0(new_n48), .i1(i2), .o(new_n71));
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INV1 g37(.i0(new_n71), .o(new_n72));
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AND2 g38(.i0(new_n72), .i1(new_n70), .o(new_n73));
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INV1 g39(.i0(new_n73), .o(new_n74));
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AND2 g40(.i0(new_n74), .i1(new_n55), .o(new_n75));
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INV1 g41(.i0(new_n75), .o(new_n76));
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AND2 g42(.i0(new_n73), .i1(\o[14] ), .o(new_n77));
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INV1 g43(.i0(new_n77), .o(new_n78));
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AND2 g44(.i0(new_n78), .i1(new_n76), .o(new_n79));
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INV1 g45(.i0(new_n79), .o(\o[16] ));
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AND2 g46(.i0(\o[5] ), .i1(new_n45), .o(\o[21] ));
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INV1 g47(.i0(\o[21] ), .o(\o[17] ));
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AND2 g48(.i0(i3), .i1(i2), .o(new_n83));
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INV1 g49(.i0(new_n83), .o(new_n84));
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AND2 g50(.i0(new_n84), .i1(\o[5] ), .o(\o[22] ));
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INV1 g51(.i0(\o[22] ), .o(\o[18] ));
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AND2 g52(.i0(\o[8] ), .i1(i2), .o(\o[19] ));
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AND2 g53(.i0(new_n48), .i1(new_n45), .o(new_n88));
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INV1 g54(.i0(new_n88), .o(new_n89));
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AND2 g55(.i0(new_n89), .i1(\o[8] ), .o(\o[20] ));
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INV1 g56(.i0(\o[19] ), .o(\o[23] ));
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INV1 g57(.i0(\o[20] ), .o(\o[24] ));
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AND2 g58(.i0(\o[5] ), .i1(new_n48), .o(new_n93));
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AND2 g59(.i0(new_n93), .i1(new_n45), .o(\o[27] ));
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INV1 g60(.i0(\o[27] ), .o(\o[25] ));
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AND2 g61(.i0(\o[8] ), .i1(i3), .o(new_n96));
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AND2 g62(.i0(new_n96), .i1(i2), .o(\o[26] ));
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INV1 g63(.i0(\o[26] ), .o(\o[28] ));
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AND2 g64(.i0(new_n45), .i1(i0), .o(new_n99));
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INV1 g65(.i0(new_n99), .o(new_n100));
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AND2 g66(.i0(new_n100), .i1(new_n58), .o(new_n101));
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INV1 g67(.i0(new_n101), .o(\o[29] ));
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BUF1 g68(.i0(i0), .o(\o[0] ));
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endmodule
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@@ -0,0 +1,49 @@
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module all_kyupy_primitives (i0, i1, i2, i3, o);
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input i0;
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input i1;
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input i2;
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input i3;
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output [29:0] o;
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BUF1 buf1_0 (.i0(i0), .o(o[0]));
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INV1 inv1_0 (.i0(i1), .o(o[1]));
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AND2 and2_0 (.i0(i0), .i1(i1), .o(o[2]));
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AND3 and3_0 (.i0(i0), .i1(i1), .i2(i2), .o(o[3]));
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AND4 and4_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[4]));
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NAND2 nand2_0 (.i0(i0), .i1(i1), .o(o[5]));
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NAND3 nand3_0 (.i0(i0), .i1(i1), .i2(i2), .o(o[6]));
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NAND4 nand4_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[7]));
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OR2 or2_0 (.i0(i0), .i1(i1), .o(o[8]));
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OR3 or3_0 (.i0(i0), .i1(i1), .i2(i2), .o(o[9]));
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OR4 or4_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[10]));
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NOR2 nor2_0 (.i0(i0), .i1(i1), .o(o[11]));
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NOR3 nor3_0 (.i0(i0), .i1(i1), .i2(i2), .o(o[12]));
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NOR4 nor4_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[13]));
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XOR2 xor2_0 (.i0(i0), .i1(i1), .o(o[14]));
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XOR3 xor3_0 (.i0(i0), .i1(i1), .i2(i2), .o(o[15]));
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XOR4 xor4_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[16]));
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AO21 ao21_0 (.i0(i0), .i1(i1), .i2(i2), .o(o[17]));
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AO22 ao22_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[18]));
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OA21 oa21_0 (.i0(i0), .i1(i1), .i2(i2), .o(o[19]));
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OA22 oa22_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[20]));
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AOI21 aoi21_0 (.i0(i0), .i1(i1), .i2(i2), .o(o[21]));
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AOI22 aoi22_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[22]));
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OAI21 oai21_0 (.i0(i0), .i1(i1), .i2(i2), .o(o[23]));
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OAI22 oai22_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[24]));
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AO211 ao211_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[25]));
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OA211 oa211_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[26]));
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AOI211 aoi211_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[27]));
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OAI211 oai211_0 (.i0(i0), .i1(i1), .i2(i2), .i3(i3), .o(o[28]));
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MUX21 mux21_0 (.i0(i0), .i1(i1), .i2(i2), .o(o[29]));
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endmodule
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@@ -0,0 +1,34 @@
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# library of all KyuPy simulation primitives defined in kyupy.sim
|
||||||
|
GATE BUF1 1 o=i0; PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE INV1 1 o=!i0; PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE AND2 1 o=i0*i1; PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE AND3 1 o=i0*i1*i2; PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE AND4 1 o=i0*i1*i2*i3; PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE NAND2 1 o=!(i0*i1); PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE NAND3 1 o=!(i0*i1*i2); PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE NAND4 1 o=!(i0*i1*i2*i3); PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE OR2 1 o=i0+i1; PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE OR3 1 o=i0+i1+i2; PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE OR4 1 o=i0+i1+i2+i3; PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE NOR2 1 o=!(i0+i1); PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE NOR3 1 o=!(i0+i1+i2); PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE NOR4 1 o=!(i0+i1+i2+i3); PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE XOR2 1 o=i0^i1; PIN * UNKNOWN 1 999 1 0 1 0
|
||||||
|
GATE XOR3 1 o=i0^i1^i2; PIN * UNKNOWN 1 999 1 0 1 0
|
||||||
|
GATE XOR4 1 o=i0^i1^i2^i3; PIN * UNKNOWN 1 999 1 0 1 0
|
||||||
|
GATE XNOR2 1 o=!(i0^i1); PIN * UNKNOWN 1 999 1 0 1 0
|
||||||
|
GATE XNOR3 1 o=!(i0^i1^i2); PIN * UNKNOWN 1 999 1 0 1 0
|
||||||
|
GATE XNOR4 1 o=!(i0^i1^i2^i3); PIN * UNKNOWN 1 999 1 0 1 0
|
||||||
|
GATE AO21 1 o=(i0*i1)+i2; PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE AO22 1 o=(i0*i1)+(i2*i3); PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE OA21 1 o=(i0+i1)*i2; PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE OA22 1 o=(i0+i1)*(i2+i3); PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE AOI21 1 o=!( (i0*i1)+i2 ); PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE AOI22 1 o=!( (i0*i1)+(i2*i3) ); PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE OAI21 1 o=!( (i0+i1)*i2 ); PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE OAI22 1 o=!( (i0+i1)*(i2+i3) ); PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE AO211 1 o=(i0*i1)+i2+i3; PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE OA211 1 o=(i0+i1)*i2*i3; PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE AOI211 1 o=!( (i0*i1)+i2+i3 ); PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE OAI211 1 o=!( (i0+i1)*i2*i3 ); PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE MUX21 1 o=(i0*!i2)+(i1*i2); PIN * UNKNOWN 1 999 1 0 1 0
|
||||||
@@ -0,0 +1,6 @@
|
|||||||
|
read kyupy_simprims.genlib
|
||||||
|
read -m all_kyupy_simprims.v
|
||||||
|
fraig
|
||||||
|
read minimal.genlib
|
||||||
|
map
|
||||||
|
write all_kyupy_simprims.minimal.v
|
||||||
@@ -0,0 +1,5 @@
|
|||||||
|
# A minimal library for generating logically equivalent circuits with
|
||||||
|
# minimum number of gate types.
|
||||||
|
GATE BUF1 1 o=i0; PIN * NONINV 1 999 1 0 1 0
|
||||||
|
GATE INV1 1 o=!i0; PIN * INV 1 999 1 0 1 0
|
||||||
|
GATE AND2 1 o=i0*i1; PIN * NONINV 1 999 1 0 1 0
|
||||||
+17
-2
@@ -1,7 +1,7 @@
|
|||||||
import numpy as np
|
import numpy as np
|
||||||
|
|
||||||
from kyupy.logic_sim import LogicSim, LogicSim6V
|
from kyupy.logic_sim import LogicSim, LogicSim2V, LogicSim6V
|
||||||
from kyupy import bench, logic, sim
|
from kyupy import bench, logic, sim, verilog
|
||||||
from kyupy.logic import mvarray, bparray, bp_to_mv, mv_to_bp
|
from kyupy.logic import mvarray, bparray, bp_to_mv, mv_to_bp
|
||||||
|
|
||||||
def assert_equal_shape_and_contents(actual, desired):
|
def assert_equal_shape_and_contents(actual, desired):
|
||||||
@@ -9,6 +9,21 @@ def assert_equal_shape_and_contents(actual, desired):
|
|||||||
assert actual.shape == desired.shape
|
assert actual.shape == desired.shape
|
||||||
np.testing.assert_allclose(actual, desired)
|
np.testing.assert_allclose(actual, desired)
|
||||||
|
|
||||||
|
def test_simprims(mydir):
|
||||||
|
c1 = verilog.load(mydir / 'all_kyupy_simprims.v')
|
||||||
|
c2 = verilog.load(mydir / 'all_kyupy_simprims.minimal.v')
|
||||||
|
pi_count = sum([len(n.ins)==0 for n in c1.io_nodes])
|
||||||
|
sim1 = LogicSim2V(c1, sims=2**pi_count)
|
||||||
|
sim2 = LogicSim2V(c2, sims=2**pi_count)
|
||||||
|
tests1 = sim1.allocate()
|
||||||
|
tests1[sim1.pippi_s_locs] = np.fromfunction(lambda x, y: logic.ONE * ((2**x & y) != 0), (pi_count, sim1.sims), dtype=int) # exhaustive test
|
||||||
|
tests2 = tests1.copy()
|
||||||
|
sim1.simulate(tests1)
|
||||||
|
sim2.simulate(tests2)
|
||||||
|
np.testing.assert_array_equal(
|
||||||
|
tests1[c1.io_locs('o')],
|
||||||
|
tests2[c2.io_locs('o')])
|
||||||
|
|
||||||
def test_2v():
|
def test_2v():
|
||||||
c = bench.parse(f'''
|
c = bench.parse(f'''
|
||||||
input(i3, i2, i1, i0)
|
input(i3, i2, i1, i0)
|
||||||
|
|||||||
Reference in new issue
Block a user