correct timing padding
This commit is contained in:
1 parent
fc8e65e788
commit
02f3a0e1b2
2 files changed
+6
-6
No files matched your search
+5
-5
@@ -169,7 +169,7 @@ class SimOps:
|
|||||||
self.tmp_idx = self.zero_idx + 1
|
self.tmp_idx = self.zero_idx + 1
|
||||||
self.ppi_offset = self.tmp_idx + 1
|
self.ppi_offset = self.tmp_idx + 1
|
||||||
self.ppo_offset = self.ppi_offset + len(self.s_nodes)
|
self.ppo_offset = self.ppi_offset + len(self.s_nodes)
|
||||||
self.vat_length = self.ppo_offset + len(self.s_nodes)
|
self.vat_len = self.ppo_offset + len(self.s_nodes)
|
||||||
|
|
||||||
# translate circuit structure into self.ops
|
# translate circuit structure into self.ops
|
||||||
ops = []
|
ops = []
|
||||||
@@ -217,7 +217,7 @@ class SimOps:
|
|||||||
self.ops = np.asarray(ops, dtype='int32')
|
self.ops = np.asarray(ops, dtype='int32')
|
||||||
|
|
||||||
# create a map from fanout lines to stem lines for fork stripping
|
# create a map from fanout lines to stem lines for fork stripping
|
||||||
stems = np.zeros(self.vat_length, dtype='int32') - 1 # default to -1: 'no fanout line'
|
stems = np.zeros(self.vat_len, dtype='int32') - 1 # default to -1: 'no fanout line'
|
||||||
if strip_forks:
|
if strip_forks:
|
||||||
for f in circuit.forks.values():
|
for f in circuit.forks.values():
|
||||||
prev_line = f.ins[0]
|
prev_line = f.ins[0]
|
||||||
@@ -228,8 +228,8 @@ class SimOps:
|
|||||||
stems[ol] = stem_idx
|
stems[ol] = stem_idx
|
||||||
|
|
||||||
# calculate level (distance from PI/PPI) and reference count for each line
|
# calculate level (distance from PI/PPI) and reference count for each line
|
||||||
levels = np.zeros(self.vat_length, dtype='int32')
|
levels = np.zeros(self.vat_len, dtype='int32')
|
||||||
ref_count = np.zeros(self.vat_length, dtype='int32')
|
ref_count = np.zeros(self.vat_len, dtype='int32')
|
||||||
level_starts = [0]
|
level_starts = [0]
|
||||||
current_level = 1
|
current_level = 1
|
||||||
for i, op in enumerate(self.ops):
|
for i, op in enumerate(self.ops):
|
||||||
@@ -250,7 +250,7 @@ class SimOps:
|
|||||||
self.level_stops = np.asarray(level_starts[1:] + [len(self.ops)], dtype='int32')
|
self.level_stops = np.asarray(level_starts[1:] + [len(self.ops)], dtype='int32')
|
||||||
|
|
||||||
# state allocation table. maps line and interface indices to self.state memory locations
|
# state allocation table. maps line and interface indices to self.state memory locations
|
||||||
self.vat = np.zeros((self.vat_length, 3), dtype='int')
|
self.vat = np.zeros((self.vat_len, 3), dtype='int')
|
||||||
self.vat[:, 0] = -1
|
self.vat[:, 0] = -1
|
||||||
|
|
||||||
h = Heap()
|
h = Heap()
|
||||||
|
|||||||
@@ -56,7 +56,7 @@ class WaveSim(SimOps):
|
|||||||
self.c_len *= 4
|
self.c_len *= 4
|
||||||
self.vat[...,0:2] *= 4
|
self.vat[...,0:2] *= 4
|
||||||
|
|
||||||
self.timing = np.zeros((self.c_len, 2, 2))
|
self.timing = np.zeros((self.vat_len, 2, 2))
|
||||||
self.timing[:len(timing)] = timing
|
self.timing[:len(timing)] = timing
|
||||||
|
|
||||||
self.c = np.zeros((self.c_len, sims), dtype=np.float32) + TMAX
|
self.c = np.zeros((self.c_len, sims), dtype=np.float32) + TMAX
|
||||||
|
|||||||
Reference in new issue
Block a user