A python module for parsing, processing, and simulating gate-level circuits.
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from kyupy import stil, verilog
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from kyupy.techlib import SAED32
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def test_b15(mydir):
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b15 = verilog.load(mydir / 'b15_2ig.v.gz', tlib=SAED32)
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s = stil.load(mydir / 'b15_2ig.sa_nf.stil.gz')
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assert len(s.signal_groups) == 10
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assert len(s.scan_chains) == 1
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assert len(s.calls) == 1357
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tests = s.tests(b15)
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resp = s.responses(b15)
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assert len(tests) > 0
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assert len(resp) > 0
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s2 = stil.load(mydir / 'b15_2ig.tf_nf.stil.gz')
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tests = s2.tests_loc(b15)
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resp = s2.responses(b15)
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assert len(tests) > 0
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assert len(resp) > 0
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