A python module for parsing, processing, and simulating gate-level circuits.
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(DELAYFILE
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(SDFVERSION "OVI 2.1")
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(DESIGN "gates")
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(DIVIDER /)
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(VOLTAGE 1.20:1.20:1.20)
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(PROCESS "TYPICAL")
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(TEMPERATURE 25.00:25.00:25.00)
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(TIMESCALE 1ns)
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(CELL
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(CELLTYPE "NAND2_X1")
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(INSTANCE nandgate)
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(DELAY
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(ABSOLUTE
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(IOPATH A1 ZN (0.099:0.103:0.103) (0.122:0.127:0.127))
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(IOPATH A2 ZN (0.083:0.086:0.086) (0.100:0.104:0.104))
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)
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)
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)
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(CELL
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(CELLTYPE "AND2_X1")
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(INSTANCE andgate)
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(DELAY
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(ABSOLUTE
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(IOPATH A1 ZN (0.367:0.378:0.378) (0.351:0.377:0.377))
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(IOPATH A2 ZN (0.366:0.375:0.375) (0.359:0.370:0.370))
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)
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)
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)
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(CELL
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(CELLTYPE "OAI21_X1")
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(INSTANCE oai21gate)
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(DELAY
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(ABSOLUTE
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(IOPATH B1 ZN (0.000:0.025:0.025) (0.000:0.013:0.013))
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(IOPATH B2 ZN (0.000:0.030:0.030) (0.000:0.016:0.016))
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( COND (B1 == 1'b0) && (B2 == 1'b1) (IOPATH A ZN (0.000:0.018:0.018)))
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(COND (B1 == 1'b1) && (B2 == 1'b0) (IOPATH A ZN (0.000:0.018:0.018) (0.000:0.016:0.016)))
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(COND (B1 == 1'b1) && (B2 == 1'b1) (IOPATH A ZN (0.000:0.019:0.019) (0.000:0.014:0.014)))
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)
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)
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)
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(CELL
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(CELLTYPE "MUX2_X1")
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(INSTANCE mux2gate)
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(DELAY
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(ABSOLUTE
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(COND (B == 1'b0) && (S == 1'b0) (IOPATH A Z (0.000:0.037:0.037) (0.000:0.058:0.058)))
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(COND (B == 1'b1) && (S == 1'b0) (IOPATH A Z (0.000:0.037:0.037) (0.000:0.058:0.058)))
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(COND (A == 1'b0) && (S == 1'b1) (IOPATH B Z (0.000:0.035:0.035) (0.000:0.056:0.056)))
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(COND (A == 1'b1) && (S == 1'b1) (IOPATH B Z (0.000:0.035:0.035) (0.000:0.056:0.056)))
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(COND (A == 1'b0) && (B == 1'b1) (IOPATH S Z (0.000:0.047:0.047) (0.000:0.073:0.073)))
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(COND (A == 1'b1) && (B == 1'b0) (IOPATH S Z (0.000:0.072:0.072) (0.000:0.064:0.064)))
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)
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)
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)
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)
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