A python module for parsing, processing, and simulating gate-level circuits.
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
|
|
|
|
import pytest
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
@pytest.fixture(scope='session')
|
|
|
|
|
def mydir():
|
|
|
|
|
import os
|
|
|
|
|
from pathlib import Path
|
|
|
|
|
return Path(os.path.realpath(os.path.join(os.getcwd(), os.path.dirname(__file__))))
|
|
|
|
|
|
|
|
|
|
@pytest.fixture(scope='session')
|
|
|
|
|
def b14_circuit(mydir):
|
|
|
|
|
from kyupy import verilog
|
|
|
|
|
return verilog.load(mydir / 'b14.v.gz', branchforks=True)
|
|
|
|
|
|
|
|
|
|
@pytest.fixture(scope='session')
|
|
|
|
|
def b14_delays(mydir, b14_circuit):
|
|
|
|
|
from kyupy import sdf
|
|
|
|
|
return sdf.load(mydir / 'b14.sdf.gz').iopaths(b14_circuit)[1:2]
|
