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import pickle
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from kyupy.circuit import Circuit, Node, Line
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from kyupy import verilog
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def test_lines():
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c = Circuit()
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n1 = Node(c, 'n1')
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n2 = Node(c, 'n2')
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line = Line(c, n1, n2)
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assert line.driver == n1
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assert line.reader == n2
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assert line.driver_pin == 0
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assert line.reader_pin == 0
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assert n1.outs[0] == line
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assert n2.ins[0] == line
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line2 = Line(c, n1, (n2, 2))
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assert line2.driver == n1
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assert line2.reader == n2
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assert line2.driver_pin == 1
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assert line2.reader_pin == 2
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assert n1.outs[0] == line
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assert n1.outs[1] == line2
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assert n2.ins[1] is None
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assert n2.ins[2] == line2
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line3 = Line(c, n1, n2)
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assert line3.driver_pin == 2
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assert line3.reader_pin == 1
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assert n1.outs[2] == line3
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assert n2.ins[1] == line3
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assert n2.ins[2] == line2
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assert len(c.lines) == 3
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line3.remove()
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assert len(c.lines) == 2
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assert c.lines[0].index == 0
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assert c.lines[1].index == 1
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assert n1.outs[2] is None
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assert n2.ins[1] is None
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assert n2.ins[2] == line2
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def test_circuit():
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c = Circuit()
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in1 = Node(c, 'in1', 'buf')
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in2 = Node(c, 'in2', 'buf')
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out1 = Node(c, 'out1', 'buf')
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assert 'in1' in c.cells
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assert 'and1' not in c.cells
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c.interface[0] = in1
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c.interface[1] = in2
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c.interface[2] = out1
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and1 = Node(c, 'and1', kind='and')
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Line(c, in1, and1)
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Line(c, in2, and1)
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Line(c, and1, out1)
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assert len(in1.ins) == 0
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assert len(in1.outs) == 1
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assert len(in2.outs) == 1
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assert in1.outs[0].reader == and1
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assert in1.outs[0].driver == in1
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assert len(and1.ins) == 2
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assert len(and1.outs) == 1
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or1 = Node(c, 'or1', 'or')
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Line(c, and1, (or1, 1))
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or2 = Node(c, 'or2', 'or')
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or3 = Node(c, 'or3', 'or')
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assert or2.index == 5
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assert or3.index == 6
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assert len(c.nodes) == 7
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or2.remove()
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or3 = c.cells['or3']
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assert or3.index == 5
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assert 'or2' not in c.cells
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assert len(c.nodes) == 6
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c.cells['or3'].remove()
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assert 'or3' not in c.cells
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assert len(c.nodes) == 5
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repr(c)
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str(c)
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for n in c.topological_order():
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repr(n)
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def test_pickle(mydir):
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c = verilog.load(mydir / 'b14.v.gz')
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assert c is not None
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cs = pickle.dumps(c)
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assert cs is not None
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c2 = pickle.loads(cs)
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assert c == c2
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