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48 lines
852 B
48 lines
852 B
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# |
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# jpeg_core config |
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# |
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JPEG_CORE_VVP := jpeg_core_tb.vvp |
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JPEG_CORE_INFILE ?= test.jpg |
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JPEG_CORE_OUTFILE ?= output.ppm |
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JPEG_CORE_VVP_FLAGS ?= |
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JPEG_CORE_DIR := core_jpeg/src_v |
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JPEG_CORE_SRCS := $(wildcard $(JPEG_CORE_DIR)/*.v) |
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JPEG_CORE_TB := jpeg_core_tb.v |
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# |
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# General targets |
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# |
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.PHONY: all jpeg_rtl_sim clean |
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all: $(JPEG_CORE_VVP) |
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clean: |
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rm -f $(JPEG_CORE_VVP) $(JPEG_CORE_OUTFILE) *.vcd |
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# |
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# jpeg_core targets |
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# |
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$(JPEG_CORE_VVP): $(JPEG_CORE_TB) $(JPEG_CORE_SRCS) |
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iverilog -g2005 -Wall -o $@ $^ |
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# Run RTL simulation |
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jpeg_rtl_sim: $(JPEG_CORE_VVP) |
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vvp $< $(JPEG_CORE_VVP_FLAGS) +infile=$(JPEG_CORE_INFILE) +outfile=$(JPEG_CORE_OUTFILE) |
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# |
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# picorv32 targets |
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# |
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test_vcd: |
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make -C picorv32 test_vcd |
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test_ez_vcd: |
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make -C picorv32 test_ez_vcd |
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testbench.npy: |
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./picorv32_vcd_import.py picorv32/testbench.vcd testbench.npy
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