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65 lines
1.5 KiB
65 lines
1.5 KiB
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# |
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# picorv32 / sbst config |
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# |
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SBST_SRCS := $(wildcard sbst_programs/*.c) |
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# |
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# jpeg_core config |
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# |
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JPEG_CORE_VVP := jpeg_core_tb.vvp |
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JPEG_CORE_INFILE ?= test.jpg |
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JPEG_CORE_OUTFILE ?= output.ppm |
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JPEG_CORE_VVP_FLAGS ?= |
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JPEG_CORE_DIR := core_jpeg/src_v |
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JPEG_CORE_SRCS := $(wildcard $(JPEG_CORE_DIR)/*.v) |
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JPEG_CORE_TB := jpeg_core_tb.v |
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# |
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# General targets |
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# |
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.PHONY: all jpeg_rtl_sim clean |
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all: $(JPEG_CORE_VVP) |
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clean: |
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rm -f $(JPEG_CORE_VVP) $(JPEG_CORE_OUTFILE) *.vcd $(SBST_SRCS:.c=.bin) $(SBST_SRCS:.c=.hex) |
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# |
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# jpeg_core targets |
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# |
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$(JPEG_CORE_VVP): $(JPEG_CORE_TB) $(JPEG_CORE_SRCS) |
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iverilog -g2005 -Wall -o $@ $^ |
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# Run RTL simulation |
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jpeg_rtl_sim: $(JPEG_CORE_VVP) |
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vvp $< $(JPEG_CORE_VVP_FLAGS) +infile=$(JPEG_CORE_INFILE) +outfile=$(JPEG_CORE_OUTFILE) |
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# |
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# picorv32 targets |
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# |
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test_vcd: |
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make -C picorv32 test_vcd |
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test_ez_vcd: |
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make -C picorv32 test_ez_vcd |
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testbench.npy: |
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./picorv32_vcd_import.py picorv32/testbench.vcd testbench.npy |
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sbst_programs: $(SBST_SRCS:.c=.bin) $(SBST_SRCS:.c=.hex) |
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sbst_programs/%.elf: sbst_programs/%.c sbst_programs/start.S |
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riscv64-unknown-elf-gcc -march=rv32ima_zicsr -mabi=ilp32 -ffreestanding -O0 -nostdlib -o $@ $^ -T picorv32/firmware/riscv.ld |
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sbst_programs/%.bin: sbst_programs/%.elf |
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riscv64-unknown-elf-objcopy -O binary $^ $@ |
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sbst_programs/%.hex: sbst_programs/%.bin |
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python3 -c "import os; d=open('$^','rb').read(); [print('{:02x}{:02x}{:02x}{:02x}'.format(d[i+3],d[i+2],d[i+1],d[i])) for i in range(0,len(d),4)]" > $@
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