#
# picorv32 / sbst config
#

SBST_SRCS := $(wildcard sbst_programs/*.c)

#
# jpeg_core config
#

JPEG_CORE_VVP       := jpeg_core_tb.vvp
JPEG_CORE_INFILE    ?= test.jpg
JPEG_CORE_OUTFILE   ?= output.ppm
JPEG_CORE_VVP_FLAGS ?=

JPEG_CORE_DIR    := core_jpeg/src_v
JPEG_CORE_SRCS   := $(wildcard $(JPEG_CORE_DIR)/*.v)
JPEG_CORE_TB     := jpeg_core_tb.v

#
# General targets
#

.PHONY: all jpeg_rtl_sim clean

all: $(JPEG_CORE_VVP)

clean:
	rm -f $(JPEG_CORE_VVP) $(JPEG_CORE_OUTFILE) *.vcd $(SBST_SRCS:.c=.bin) $(SBST_SRCS:.c=.hex)

#
# jpeg_core targets
#

$(JPEG_CORE_VVP): $(JPEG_CORE_TB) $(JPEG_CORE_SRCS)
	iverilog -g2005 -Wall -o $@ $^

# Run RTL simulation
jpeg_rtl_sim: $(JPEG_CORE_VVP)
	vvp $< $(JPEG_CORE_VVP_FLAGS) +infile=$(JPEG_CORE_INFILE) +outfile=$(JPEG_CORE_OUTFILE)

#
# picorv32 targets
#

test_vcd:
	make -C picorv32 test_vcd

test_ez_vcd:
	make -C picorv32 test_ez_vcd

testbench.npy:
	./picorv32_vcd_import.py picorv32/testbench.vcd testbench.npy

sbst_programs: $(SBST_SRCS:.c=.bin) $(SBST_SRCS:.c=.hex)

sbst_programs/%.elf: sbst_programs/%.c sbst_programs/start.S
	riscv64-unknown-elf-gcc -march=rv32ima_zicsr -mabi=ilp32 -ffreestanding -O0 -nostdlib -o $@ $^ -T picorv32/firmware/riscv.ld

sbst_programs/%.bin: sbst_programs/%.elf
	riscv64-unknown-elf-objcopy -O binary $^ $@

sbst_programs/%.hex: sbst_programs/%.bin
	python3 -c "import os; d=open('$^','rb').read(); [print('{:02x}{:02x}{:02x}{:02x}'.format(d[i+3],d[i+2],d[i+1],d[i])) for i in range(0,len(d),4)]" > $@