#
# jpeg_core config
#

JPEG_CORE_VVP       := jpeg_core_tb.vvp
JPEG_CORE_INFILE    ?= test.jpg
JPEG_CORE_OUTFILE   ?= output.ppm
JPEG_CORE_VVP_FLAGS ?=

JPEG_CORE_DIR    := core_jpeg/src_v
JPEG_CORE_SRCS   := $(wildcard $(JPEG_CORE_DIR)/*.v)
JPEG_CORE_TB     := jpeg_core_tb.v

#
# General targets
#

.PHONY: all jpeg_rtl_sim clean

all: $(JPEG_CORE_VVP)

clean:
	rm -f $(JPEG_CORE_VVP) $(JPEG_CORE_OUTFILE) *.vcd

#
# jpeg_core targets
#

$(JPEG_CORE_VVP): $(JPEG_CORE_TB) $(JPEG_CORE_SRCS)
	iverilog -g2005 -Wall -o $@ $^

# Run RTL simulation
jpeg_rtl_sim: $(JPEG_CORE_VVP)
	vvp $< $(JPEG_CORE_VVP_FLAGS) +infile=$(JPEG_CORE_INFILE) +outfile=$(JPEG_CORE_OUTFILE)

#
# picorv32 targets
#

picorv32_rtl_sim:
	make -C picorv32 test_vcd
	cp picorv32/testbench.vcd picorv32.vcd