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62 lines
1.7 KiB
62 lines
1.7 KiB
from kyupy import bench |
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from kyupy.techlib import KYUPY |
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from fsim.static import LineRoles |
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def test_trivial_inv(): |
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c = bench.parse('input(i) output(o) o=INV(i)') |
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lr = LineRoles(c, KYUPY) |
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assert len(lr.line2roles) == 2 |
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assert len(lr.roles2lines[LineRoles.LOGIC_OUT]) == 2 |
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def test_input_fanout(): |
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c = bench.parse('input(i) output(o1) output(o2) o1=INV(i) o2=INV(i)') |
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lr = LineRoles(c, KYUPY) |
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assert len(lr.line2roles) == 4 |
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assert len(lr.roles2lines[LineRoles.LOGIC_OUT]) == 4 |
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def test_fanout(): |
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c = bench.parse('input(i) output(o1) output(o2) ii=INV(i) o1=INV(ii) o2=INV(ii)') |
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lr = LineRoles(c, KYUPY) |
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assert len(lr.line2roles) == 6 |
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assert len(lr.roles2lines[LineRoles.LOGIC_OUT]) == 6 |
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def test_s27(): |
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# bench parser does not add any clock or set/reset logic. |
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c = bench.parse(''' |
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# 1 outputs |
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# 3 D-type flipflops |
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# 2 inverters |
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# 8 gates (1 ANDs + 1 NANDs + 2 ORs + 4 NORs) |
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INPUT(G0) |
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INPUT(G1) |
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INPUT(G2) |
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INPUT(G3) |
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OUTPUT(G17) |
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G5 = DFF(G10) |
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G6 = DFF(G11) |
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G7 = DFF(G13) |
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G14 = NOT(G0) |
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G17 = NOT(G11) |
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G8 = AND(G14, G6) |
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G15 = OR(G12, G8) |
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G16 = OR(G3, G8) |
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G9 = NAND(G16, G15) |
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G10 = NOR(G14, G11) |
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G11 = NOR(G5, G9) |
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G12 = NOR(G1, G7) |
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G13 = NOR(G2, G12) |
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''') |
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lr = LineRoles(c, KYUPY) |
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assert len(lr.line2roles) == 34 # total number of signal lines in circuit |
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# 2 + 9 + 23 = 34 |
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assert len(lr.roles2lines[LineRoles.LOGIC_OUT]) == 2 |
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assert len(lr.roles2lines[LineRoles.LOGIC_SEQ]) == 9 |
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assert len(lr.roles2lines[LineRoles.LOGIC_OUT|LineRoles.LOGIC_SEQ]) == 23
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