basic project setup, tools and fsim
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"""A set of tools for static (structural) analysis of gate-level circuits.
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"""
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from collections import defaultdict
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from itertools import product
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import numpy as np
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from kyupy.circuit import Circuit, Node
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from kyupy.techlib import TechLib
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class LineRoles:
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"""Computes signal line roles of a circuit depending on the structural reach of each signal.
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The possible roles are any combination of the following:
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- 'lout' / LOGIC_OUT: there is a structural path to a primary output via zero or more combinational gates.
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- 'lseq' / LOGIC_SEQ: there is a structural path to a D input of a sequential cell via zero or more combinational gates.
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- 'clk' / CLOCK: there is a structural path to a clock input of a sequential cell via zero or more combinational gates.
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- 'rst' / RESET: there is a structural path to an asynchronous set or reset input of a sequential cell via zero or more combinational gates.
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- 'dft' / DFT: there is a structural path to an scan-in or scan-enable input of a sequential cell via zero or more combinational gates.
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Signal lines that may propagate to various cells may have multiple roles.
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The roles are encoded using bit positions in integers.
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The corresponding masks are defines as class constants LOGIC_OUT, LOGIC_SEQ, etc.
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"""
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LOGIC_OUT = 1
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LOGIC_SEQ = 2
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CLOCK = 4
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RESET = 8
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DFT = 16
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def __init__(self, circuit: Circuit, tlib: TechLib):
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self.line2roles = np.zeros(len(circuit.lines), dtype=np.uint8)
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"""Array of roles for each line index in the circuit.
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"""
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outputs = {n for n in circuit.io_nodes if len(n.ins) > 0}
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for n in circuit.reversed_topological_order(tlib):
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if tlib.is_dff(n.kind):
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for il in n.ins.without_nones():
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pname = tlib.pin_name(n.kind, il.reader_pin)
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if pname == 'D': self.line2roles[il] = self.LOGIC_SEQ
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elif pname in ('CK', 'CLK', 'CLK_N'): self.line2roles[il] = self.CLOCK
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elif pname in ('SET_B', 'RESET_B', 'SETB', 'RSTB', 'RN', 'SN'): self.line2roles[il] = self.RESET
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elif pname in ('SCD', 'SCE', 'SE', 'SI'): self.line2roles[il] = self.DFT
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else: raise ValueError(f'Unable to classify pin name "{pname}" for "{n.kind}".')
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elif n in outputs: # or len(n.outs) == 0:
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for il in n.ins.without_nones():
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self.line2roles[il] = self.LOGIC_OUT
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else:
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lc = 0
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for ol in n.outs.without_nones():
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lc |= self.line2roles[ol]
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for il in n.ins.without_nones():
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self.line2roles[il] = lc
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self.roles2lines: defaultdict[int,set[int]] = defaultdict(set)
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"""A dictionary that maps a role combination to a set of line indices matching that role combination.
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"""
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for li, lc in enumerate(self.line2roles):
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self.roles2lines[lc].add(li)
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@classmethod
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def roles_str(cls, roles: int) -> str:
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"""Returns a human-readable string for a role combination given as int.
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"""
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roles_list = [n for v, n in (
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(cls.LOGIC_OUT, 'lout'),
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(cls.LOGIC_SEQ, 'lseq'),
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(cls.CLOCK, 'clk'),
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(cls.RESET, 'rst'),
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(cls.DFT, 'dft')) if (roles&v) != 0]
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return 'none' if len(roles_list) == 0 else '|'.join(roles_list)
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@property
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def stats(self):
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"""A dictionary mapping each role combination to the number of matching signal lines.
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"""
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return {self.roles_str(roles): len(self.roles2lines[roles]) for roles in range(256) if len(self.roles2lines[roles]) > 0}
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class FaultSet:
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"""Computes eligible fault sites and a collapsed set of stuck-at faults for a circuit.
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Faults in this class are represented by integers of the form: `line_index * 2 + polarity`.
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Line index defines the location in the circuit, and polarity is 0 for stuck-at-0 and 1 for stuck-at-1.
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Faults sites are located only in the combinational portion of the circuit (excluding clock tree, asynchronous set/reset logic, dft/scan).
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Stuck-at faults are collapsed using basic controlling-value theory of simple gates.
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"""
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def __init__(self, circuit: Circuit, tlib: TechLib):
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lr = LineRoles(circuit, tlib)
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self.fault_sites = {l.index for l in circuit.lines
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if (lr.line2roles[l] & (lr.LOGIC_OUT|lr.LOGIC_SEQ)) # line propagates to output or sequential element
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and (
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(l.driver.kind == '__fork__' and len(l.driver.outs) > 1) # fanout branch
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or (l.driver.kind == '__fork__' and len(l.driver.ins) == 0) # primary input
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or (l.driver.kind != '__fork__' ) # gate output
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)
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}
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"""Set of line indices of all eligible fault sites. A fault site is eligible iff:
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fault effect can propagate via combinational gates (only) to outputs of to a flip-flop, AND
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(fault site is driven by a standard cell OR it is a primary input signal OR it is a branch of a fan-out).
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"""
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self.saf_set = {site*2+polarity for site, polarity in product(self.fault_sites, (0, 1))}
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"""Set of all stuck-at faults in the circuit. Each stuck-at fault is encoded as integer i with
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i & 1 being the polarity and i // 2 the circuit line index of its location.
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"""
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self.saf_equiv_classes : dict[int,set[int]] = {}
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r"""Dictionary mapping a representative stuck-at fault to its set of equivalent faults. The
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representative is always the fault closest to the circuit's outputs. The value set of
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representative f always contains at least f (:math:`f \in` saf_equiv_classes[f]).
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"""
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def collect_equivalent_faults(circuit: Circuit, fault: int) -> set:
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site = fault//2
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polarity = fault&1
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driver = circuit.lines[site].driver
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# Stop collapsing at fanout stems, primary inputs, and cells whose
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# output faults have no equivalent single-input fault (XOR/XNOR, MUX, the two-term
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# AND-OR/OR-AND cells, and sequential elements).
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if len(driver.outs) > 1 or len(driver.ins) == 0 or driver.kind in ('XOR2', 'XOR3', 'XOR4', 'XNOR2', 'XNOR3', 'XNOR4', 'MUX21', 'AO22', 'AOI22', 'OA22', 'OAI22', 'DFF', 'LATCH'): return {fault}
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if driver.kind == 'INV1': return {fault} | collect_equivalent_faults(circuit, driver.ins[0].index*2 + (1-polarity))
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if driver.kind in ('BUF1', '__fork__'): return {fault} | collect_equivalent_faults(circuit, driver.ins[0].index*2 + (polarity))
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def collapse(*faults: tuple) -> set:
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"""Collapse the output fault onto the given (input_line, stuck_value) pairs."""
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equiv = {fault}
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for site, value in faults:
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equiv |= collect_equivalent_faults(circuit, site.index*2 + value)
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return equiv
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# Simple gates: driving any input to its controlling value forces the output.
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# AND : out s-a-0 == every input s-a-0 (out s-a-1 has no equivalent)
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# NAND: out s-a-1 == every input s-a-0 (out s-a-0 has no equivalent)
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# OR : out s-a-1 == every input s-a-1 (out s-a-0 has no equivalent)
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# NOR : out s-a-0 == every input s-a-1 (out s-a-1 has no equivalent)
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if driver.kind.startswith('NAND'):
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return collapse(*((il, 0) for il in driver.ins.without_nones())) if polarity == 1 else {fault}
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if driver.kind.startswith('AND'):
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return collapse(*((il, 0) for il in driver.ins.without_nones())) if polarity == 0 else {fault}
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if driver.kind.startswith('NOR'):
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return collapse(*((il, 1) for il in driver.ins.without_nones())) if polarity == 0 else {fault}
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if driver.kind.startswith('OR'):
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return collapse(*((il, 1) for il in driver.ins.without_nones())) if polarity == 1 else {fault}
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# AND-OR / OR-AND complex gates: only the "single" (un-paired) terms force the output.
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# AO21 = (i0&i1) | i2 : out s-a-1 == i2 s-a-1
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# AOI21 = ~AO21 : out s-a-0 == i2 s-a-1
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# OA21 = (i0|i1) & i2 : out s-a-0 == i2 s-a-0
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# OAI21 = ~OA21 : out s-a-1 == i2 s-a-0
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# AO211 = (i0&i1) | i2 | i3 : out s-a-1 == i2 s-a-1, i3 s-a-1
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# AOI211= ~AO211 : out s-a-0 == i2 s-a-1, i3 s-a-1
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# OA211 = (i0|i1) & i2 & i3 : out s-a-0 == i2 s-a-0, i3 s-a-0
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# OAI211= ~OA211 : out s-a-1 == i2 s-a-0, i3 s-a-0
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if driver.kind == 'AO21': return collapse((driver.ins[2], 1)) if polarity == 1 else {fault}
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if driver.kind == 'AOI21': return collapse((driver.ins[2], 1)) if polarity == 0 else {fault}
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if driver.kind == 'OA21': return collapse((driver.ins[2], 0)) if polarity == 0 else {fault}
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if driver.kind == 'OAI21': return collapse((driver.ins[2], 0)) if polarity == 1 else {fault}
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if driver.kind == 'AO211': return collapse((driver.ins[2], 1), (driver.ins[3], 1)) if polarity == 1 else {fault}
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if driver.kind == 'AOI211': return collapse((driver.ins[2], 1), (driver.ins[3], 1)) if polarity == 0 else {fault}
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if driver.kind == 'OA211': return collapse((driver.ins[2], 0), (driver.ins[3], 0)) if polarity == 0 else {fault}
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if driver.kind == 'OAI211': return collapse((driver.ins[2], 0), (driver.ins[3], 0)) if polarity == 1 else {fault}
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raise ValueError(f'Unknown node kind {driver.kind}. Circuit should have been resolved to techlib.KYUPY?')
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remaining = self.saf_set.copy()
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circuit_resolved = circuit.copy()
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circuit_resolved.resolve_tlib_cells(tlib)
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for n in circuit.reversed_topological_order(tlib):
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for il in n.ins.without_nones():
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for polarity in (0, 1):
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repr = il.index*2+polarity
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if repr in remaining:
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equiv = collect_equivalent_faults(circuit_resolved, repr) & remaining
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remaining.difference_update(equiv)
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self.saf_equiv_classes[repr] = equiv
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self.circuit = circuit
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self.tlib = tlib
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def fault_str(self, fault: int) -> str:
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site = self.circuit.lines[fault//2]
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polarity = '@1' if fault&1 else '@0'
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if site.driver.kind == '__fork__':
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return f'{site.reader.name}/{self.tlib.pin_name(site.reader.kind, site.reader_pin)}{polarity}'
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else:
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return f'{site.driver.name}/{self.tlib.pin_name(site.driver.kind, site.driver_pin, output=True)}{polarity}'
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