stefan/fsim
1
0 Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

fix default pattern argument

Browse Source
This commit is contained in:
stefan committed 2026-06-24 19:10:18 +09:00
1 parent 9a41edda4c
commit 25a65f1ace
1 file changed
+1 -1
Download Patch File Download Diff File Expand all files Collapse all files
main.py
+1 -1
View File
@@ -17,7 +17,7 @@ def main():
parser = argparse.ArgumentParser(description='A basic stuck-at fault simulator.') parser = argparse.ArgumentParser(description='A basic stuck-at fault simulator.')
parser.add_argument('-t', '--tlib', default='SKY130', help=f'Techlib for verilog circuit. Default: SKY130, available: {sorted(techlib_by_name.keys())}.') parser.add_argument('-t', '--tlib', default='SKY130', help=f'Techlib for verilog circuit. Default: SKY130, available: {sorted(techlib_by_name.keys())}.')
parser.add_argument('-p', '--patterns', default=1024, help='Pattern file or number of random patterns to simulate. Default: 1024.') parser.add_argument('-p', '--patterns', default='1024', help='Pattern file or number of random patterns to simulate. Default: 1024.')
parser.add_argument('-o', '--output', default=None, help='') parser.add_argument('-o', '--output', default=None, help='')
parser.add_argument('--seed', type=int, default=42, help='Random seed for reproducibility. Default: 42.') parser.add_argument('--seed', type=int, default=42, help='Random seed for reproducibility. Default: 42.')
parser.add_argument('circuit', help='Gate-level verilog, bench, or nix package to import. See available packages: "nix flake show github:s-holst/benchmark-circuits".') parser.add_argument('circuit', help='Gate-level verilog, bench, or nix package to import. See available packages: "nix flake show github:s-holst/benchmark-circuits".')