diff --git a/kyupy b/kyupy
index 53309f9..f5af7ec 160000
--- a/kyupy
+++ b/kyupy
@@ -1 +1 @@
-Subproject commit 53309f9e597c91bf630886f7e125995bf48c6f53
+Subproject commit f5af7ec3d9554c35f72ed42be6719f49438201c2
diff --git a/tests/c17.bench b/tests/c17.bench
new file mode 100644
index 0000000..dbbfa8f
--- /dev/null
+++ b/tests/c17.bench
@@ -0,0 +1,21 @@
+# c17
+# 5 inputs
+# 2 outputs
+# 0 inverter
+# 6 gates ( 6 NANDs )
+
+INPUT(1)
+INPUT(2)
+INPUT(3)
+INPUT(6)
+INPUT(7)
+
+OUTPUT(22)
+OUTPUT(23)
+
+10 = NAND(1, 3)
+11 = NAND(3, 6)
+16 = NAND(2, 11)
+19 = NAND(11, 7)
+22 = NAND(10, 16)
+23 = NAND(16, 19)
\ No newline at end of file
diff --git a/tests/conftest.py b/tests/conftest.py
new file mode 100644
index 0000000..c0ac0e5
--- /dev/null
+++ b/tests/conftest.py
@@ -0,0 +1,34 @@
+import pytest
+
+@pytest.fixture(scope='session')
+def mydir():
+    import os
+    from pathlib import Path
+    return Path(os.path.realpath(os.path.join(os.getcwd(), os.path.dirname(__file__))))
+
+@pytest.fixture(scope='session')
+def s27_bench(mydir):
+    from kyupy import bench
+    # bench parser does not add any clock or set/reset logic.
+    return bench.load(mydir / 's27.bench')
+
+@pytest.fixture(scope='session')
+def c17_bench(mydir):
+    from kyupy import bench
+    # bench parser does not add any clock or set/reset logic.
+    return bench.load(mydir / 'c17.bench')
+
+def _resolved(c):
+    from kyupy.techlib import KYUPY
+    cr = c.copy()
+    cr.resolve_tlib_cells(KYUPY)
+    return cr
+
+@pytest.fixture(scope='session')
+def c17_resolved(c17_bench):
+    # tlib-resolved copy, ready for LogicSim2V / the SAF simulators.
+    return _resolved(c17_bench)
+
+@pytest.fixture(scope='session')
+def s27_resolved(s27_bench):
+    return _resolved(s27_bench)
\ No newline at end of file
diff --git a/tests/s27.bench b/tests/s27.bench
new file mode 100644
index 0000000..0ce7165
--- /dev/null
+++ b/tests/s27.bench
@@ -0,0 +1,31 @@
+# 4 inputs
+# 1 outputs
+# 3 D-type flipflops
+# 2 inverters
+# 8 gates (1 ANDs + 1 NANDs + 2 ORs + 4 NORs)
+
+INPUT(G0)
+INPUT(G1)
+INPUT(G2)
+INPUT(G3)
+
+OUTPUT(G17)
+
+G5 = DFF(G10)
+G6 = DFF(G11)
+G7 = DFF(G13)
+
+G14 = NOT(G0)
+G17 = NOT(G11)
+
+G8 = AND(G14, G6)
+
+G15 = OR(G12, G8)
+G16 = OR(G3, G8)
+
+G9 = NAND(G16, G15)
+
+G10 = NOR(G14, G11)
+G11 = NOR(G5, G9)
+G12 = NOR(G1, G7)
+G13 = NOR(G2, G12)
\ No newline at end of file
diff --git a/tests/test_fault_set.py b/tests/test_fault_set.py
index 8b69c8e..015afac 100644
--- a/tests/test_fault_set.py
+++ b/tests/test_fault_set.py
@@ -72,48 +72,15 @@ def test_aoi_oai_complex():
     # The two-term variants do not collapse onto any single input.
     assert _class_sizes('input(i0,i1,i2,i3) output(o) o=AO22(i0,i1,i2,i3)') == (1, 1)
 
-def test_s27():
-    # bench parser does not add any clock or set/reset logic.
-    c = bench.parse('''
-        # 1 outputs
-        # 3 D-type flipflops
-        # 2 inverters
-        # 8 gates (1 ANDs + 1 NANDs + 2 ORs + 4 NORs)
-
-        INPUT(G0)
-        INPUT(G1)
-        INPUT(G2)
-        INPUT(G3)
-
-        OUTPUT(G17)
-
-        G5 = DFF(G10)
-        G6 = DFF(G11)
-        G7 = DFF(G13)
-
-        G14 = NOT(G0)
-        G17 = NOT(G11)
-
-        G8 = AND(G14, G6)
-
-        G15 = OR(G12, G8)
-        G16 = OR(G3, G8)
-
-        G9 = NAND(G16, G15)
-
-        G10 = NOR(G14, G11)
-        G11 = NOR(G5, G9)
-        G12 = NOR(G1, G7)
-        G13 = NOR(G2, G12)
-    ''')
-    fs = FaultSet(c, KYUPY, c)
+def test_s27(s27_bench):
+    fs = FaultSet(s27_bench, KYUPY, s27_bench)
     assert len(fs.saf_set) == 52
     assert len(fs.saf_equiv_classes) == 32
-    g11_line = c.cells['G11'].outs[0]
+    g11_line = s27_bench.cells['G11'].outs[0]
     g11_sa_0 = g11_line.index*2
     assert g11_sa_0 in fs.saf_equiv_classes
     assert len(fs.saf_equiv_classes[g11_sa_0]) == 5  # collapse via G9
-    g15_line = c.cells['G15'].outs[0]
+    g15_line = s27_bench.cells['G15'].outs[0]
     g15_sa_0 = g15_line.index*2
     assert g15_sa_0 in fs.saf_equiv_classes[g11_sa_0]
 
diff --git a/tests/test_line_roles.py b/tests/test_line_roles.py
index 6aac89f..56a5e26 100644
--- a/tests/test_line_roles.py
+++ b/tests/test_line_roles.py
@@ -20,41 +20,8 @@ def test_fanout():
     assert len(lr.line2roles) == 6
     assert len(lr.roles2lines[LineRoles.LOGIC_OUT]) == 6
 
-def test_s27():
-    # bench parser does not add any clock or set/reset logic.
-    c = bench.parse('''
-        # 1 outputs
-        # 3 D-type flipflops
-        # 2 inverters
-        # 8 gates (1 ANDs + 1 NANDs + 2 ORs + 4 NORs)
-
-        INPUT(G0)
-        INPUT(G1)
-        INPUT(G2)
-        INPUT(G3)
-
-        OUTPUT(G17)
-
-        G5 = DFF(G10)
-        G6 = DFF(G11)
-        G7 = DFF(G13)
-
-        G14 = NOT(G0)
-        G17 = NOT(G11)
-
-        G8 = AND(G14, G6)
-
-        G15 = OR(G12, G8)
-        G16 = OR(G3, G8)
-
-        G9 = NAND(G16, G15)
-
-        G10 = NOR(G14, G11)
-        G11 = NOR(G5, G9)
-        G12 = NOR(G1, G7)
-        G13 = NOR(G2, G12)
-    ''')
-    lr = LineRoles(c, KYUPY)
+def test_s27(s27_bench):
+    lr = LineRoles(s27_bench, KYUPY)
     assert len(lr.line2roles) == 34  # total number of signal lines in circuit
     # 2 + 9 + 23 = 34
     assert len(lr.roles2lines[LineRoles.LOGIC_OUT]) == 2